ZC702+FMCOMMS3 without DMA

Did you set the dac data source to DMA (at the dac channel section register called REG_CHN_CNTRL_7[DAC_DDS_SEL])? You can use this function.

Yes, that's pretty much it.

Can you share the connections between device core and your data path? Just copy past snippets from your tcl scripts, do not share screenshots of block design, please.  

Not really, but let me ask it in a different way. 

In your initial post mentioned that you're using a custom data path:

TX IP -> FIFO -> bit slicer for generating I,Q -> AD9361

How and where did you define this data path. Did you modify the common project script or did you modify the block design in GUI?

In that case, open up the project, go to File -> Export -> Export Block Design, and export your design to a tcl file. Then attache that file to your post. It is almost impossible to evaluate a block design from a screen shot... sorry.

Hi,

Thank you for your reply.

I am using the below functions for setting the data source and and initialising DAC : 

dac_datasel(ad9361_phy,-1,DATA_SEL_DMA);

dac_init(ad9361_phy,DATA_SEL_DMA,1);

I think this is pretty much doing the things you mentioned above. Please correct me if I am wrong and give any further ideas for debugging.

#system_bd.tcl
source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms2_bd.tcl

#system_project.tcl

source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl

adi_project_create fmcomms2_zc702
adi_project_files fmcomms2_zc702 [list \
  "system_top.v" \
  "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
  "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" \
  "system_constr.xdc" ]

adi_project_run fmcomms2_zc702

#ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl

# fifo and controller (write side)

proc p_sys_wfifo {p_name m_name adc_data_width dma_data_width} {

  global ad_hdl_dir

  set p_instance [get_bd_cells $p_name]
  set c_instance [current_bd_instance .]

  current_bd_instance $p_instance

  set m_instance [create_bd_cell -type hier $m_name]
  current_bd_instance $m_instance

  create_bd_pin -dir I adc_rst
  create_bd_pin -dir I -type clk adc_clk
  create_bd_pin -dir I adc_wr
  create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
  create_bd_pin -dir O adc_wovf

  create_bd_pin -dir I -type clk dma_clk
  create_bd_pin -dir O dma_wr
  create_bd_pin -dir O -from [expr ($dma_data_width-1)] -to 0 dma_wdata
  create_bd_pin -dir I dma_wovf

  set wfifo_ctl [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 wfifo_ctl]
  set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $wfifo_ctl
  set_property -dict [list CONFIG.DMA_DATA_WIDTH $dma_data_width] $wfifo_ctl

  set wfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 wfifo_mem]
  set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $wfifo_mem
  set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $wfifo_mem
  set_property -dict [list CONFIG.Input_Data_Width $adc_data_width] $wfifo_mem
  set_property -dict [list CONFIG.Input_Depth {64}] $wfifo_mem
  set_property -dict [list CONFIG.Output_Data_Width $dma_data_width] $wfifo_mem
  set_property -dict [list CONFIG.Overflow_Flag {true}] $wfifo_mem

  connect_bd_net -net adc_rst                 [get_bd_pins adc_rst]
  connect_bd_net -net adc_clk                 [get_bd_pins adc_clk]
  connect_bd_net -net dma_clk                 [get_bd_pins dma_clk]
  connect_bd_net -net adc_rst                 [get_bd_pins wfifo_ctl/adc_rst]
  connect_bd_net -net adc_clk                 [get_bd_pins wfifo_ctl/adc_clk]
  connect_bd_net -net dma_clk                 [get_bd_pins wfifo_ctl/dma_clk]
  connect_bd_net -net adc_clk                 [get_bd_pins wfifo_mem/wr_clk]
  connect_bd_net -net dma_clk                 [get_bd_pins wfifo_mem/rd_clk]

  connect_bd_net -net adc_wr                  [get_bd_pins adc_wr]                    [get_bd_pins wfifo_ctl/adc_wr]
  connect_bd_net -net adc_wdata               [get_bd_pins adc_wdata]                 [get_bd_pins wfifo_ctl/adc_wdata]
  connect_bd_net -net adc_wovf                [get_bd_pins adc_wovf]                  [get_bd_pins wfifo_ctl/adc_wovf]
  connect_bd_net -net dma_wr                  [get_bd_pins dma_wr]                    [get_bd_pins wfifo_ctl/dma_wr]
  connect_bd_net -net dma_wdata               [get_bd_pins dma_wdata]                 [get_bd_pins wfifo_ctl/dma_wdata]
  connect_bd_net -net dma_wovf                [get_bd_pins dma_wovf]                  [get_bd_pins wfifo_ctl/dma_wovf]

  connect_bd_net -net wfifo_ctl_fifo_rst      [get_bd_pins wfifo_ctl/fifo_rst]        [get_bd_pins wfifo_mem/rst]
  connect_bd_net -net wfifo_ctl_fifo_wr       [get_bd_pins wfifo_ctl/fifo_wr]         [get_bd_pins wfifo_mem/wr_en]
  connect_bd_net -net wfifo_ctl_fifo_wdata    [get_bd_pins wfifo_ctl/fifo_wdata]      [get_bd_pins wfifo_mem/din]
  connect_bd_net -net wfifo_ctl_fifo_wovf     [get_bd_pins wfifo_ctl/fifo_wovf]       [get_bd_pins wfifo_mem/overflow]
  connect_bd_net -net wfifo_ctl_fifo_rd       [get_bd_pins wfifo_ctl/fifo_rd]         [get_bd_pins wfifo_mem/rd_en]
  connect_bd_net -net wfifo_ctl_fifo_rdata    [get_bd_pins wfifo_ctl/fifo_rdata]      [get_bd_pins wfifo_mem/dout]
  connect_bd_net -net wfifo_ctl_fifo_rempty   [get_bd_pins wfifo_ctl/fifo_rempty]     [get_bd_pins wfifo_mem/empty]

  current_bd_instance $c_instance
}

Is this what you meant?

Please find the link attached (pdf of the block design)

blockdesign

Modified the block design in GUI. Please refer the pdf of the block design attached.

block design

Sorry. Please refer to the system.tcl file 

Sorry for the late response. 

I've looked over you design, the strange thing that I saw is that you're connecting the dac data lines to the 'bit slicer', but the dac controls are connected to the FIFO directly. This can cause a data/control misalignment on the tx path. 

Please make sure that your custom modules are respecting the dac fifo interface functionality. Also you can connect an ILA to the DAC's interface and verify the data. (you ILA is not connected correctly, you should use the device clock to drive it) If that looks OK, than most likely your configuration of the core/device is not correct.

-Istvan