Now, I go thru building and checking AD FPGA AD9371 project on my development kits Arria 10 GX and ADRV9371-W / PCBZ.
My current configuration is:
Project: hdl \ projects \ adrv9371x \ a10gx
Project brunch: Master
Nios project: no-OS \ ad9371 \ sw \
NIOS branch: 2016_R2
Quartus Prime: 188.8.131.52 standard edition
Eclipse (comes with quartus): Kepler Service Release 2 Build id: 20140224-0627
I spent 2 days to debug the following error, which I found in platform_drivers.c downloaded from Git.
The symptom is: when NIOS wrote SPI configuration words to AD9528, they really get to AD9371. The reading is doing the same from AD9371. And vice versa.
The cause is: Wrong selection of CS signal in platform_drivers.c:
IOWR_32DIRECT (SPI_BASEADDR, ALT_AVL_SPI_SLAVE_SEL_REG, ~ (dev-> chip_select));
Here, no need to inverse (dev-> chip_select), because selection of active masters in slaveselect register of the Altera SPI Core is made by mask with positive logic:
CS definitions from platform_drivers.h are:
#define AD9528_CHIP_SELECT 2#define AD9371_CHIP_SELECT 1
And this is right because of pin assignments on board.
Right selection of master CS is:
IOWR_32DIRECT (SPI_BASEADDR, ALT_AVL_SPI_SLAVE_SEL_REG, dev-> chip_select);
Now I go futher and get next error:
device-> rx-> rxAgcCtrl-> agcGainUpdateTime_us out of range in MYKONOS_setupRxAgc ()
Hope, it will not take much time to debug ...
No, they are defined in system.h - it is part of the bsp. Most probably you don't use the HDL from the master branch.
Today I've tried new files from no-os master branch, and I stuck with project compilation errors: 'AD9371_RX_JESD204_LINK_MANAGEMENT_BASE' undeclared (first use in this function) jesd_core.c /software/src line 313 C/C++ Problem'AD9371_RX_JESD204_LINK_RECONFIG_BASE' undeclared (first use in this function) jesd_core.c /software/src line 441 C/C++ Problem'AD9371_RX_JESD204_LINK_RECONFIG_BASE' undeclared (first use in this function) jesd_core.c /software/src line 488 C/C++ Problem... etc 21 same errors.
I suppose those definitions should be in jesd_core.h, but there are not. Is it right?
You are not using the correct version of Quartus. Take a look here: hdl/adi_project_alt.tcl at master · analogdevicesinc/hdl · GitHub
Thank you. It is right, currently I am on 2016_R2 hdl branch.PS Dragosh, I am sorry for addressing to you by surname. I made this fault, because Bogdan - there is a such russian name.
Unfortunately, with latest code I've got same result as early:
Please wait...ATX PLL calibration OKch 0 TX termination and VOD calib OKch 1 TX termination and VOD calib OKch 2 TX termination and VOD calib OKch 3 TX termination and VOD calib OKch 0 CDR/CMU PLL & RX offset calib OKch 1 CDR/CMU PLL & RX offset calib OKch 0 CDR/CMU PLL & RX offset calib OKch 1 CDR/CMU PLL & RX offset calib OKRX_XCVR initialization OKTX_XCVR initialization OKRX_OS_XCVR initialization OKMCS successfulCLKPLL lockedAD9371 ARM version 5.1.1PLLs lockedCalibrations completed successfullyRxFramerStatus = 0x20OrxFramerStatus = 0x20DeframerStatus = 0x21dac_setup dac core initialized (122 MHz).adc_setup adc core initialized (123 MHz).Done
My current configuration is:Project: hdl\projects\adrv9371x\a10gx\Altera project brunch: MasterNo-OS project brunch: MasterQuartus Prime: 16.0.0 build 211 standart editionEclipse (comes with quartus): Version: Kepler Service Release 2 Build id: 20140224-0627