Now, I go thru building and checking AD FPGA AD9371 project on my development kits Arria 10 GX and ADRV9371-W / PCBZ.
My current configuration is:
Project: hdl \ projects \ adrv9371x \ a10gx
Project brunch: Master
Nios project: no-OS \ ad9371 \ sw \
NIOS branch: 2016_R2
Quartus Prime: 126.96.36.199 standard edition
Eclipse (comes with quartus): Kepler Service Release 2 Build id: 20140224-0627
I spent 2 days to debug the following error, which I found in platform_drivers.c downloaded from Git.
The symptom is: when NIOS wrote SPI configuration words to AD9528, they really get to AD9371. The reading is doing the same from AD9371. And vice versa.
The cause is: Wrong selection of CS signal in platform_drivers.c:
IOWR_32DIRECT (SPI_BASEADDR, ALT_AVL_SPI_SLAVE_SEL_REG, ~ (dev-> chip_select));
Here, no need to inverse (dev-> chip_select), because selection of active masters in slaveselect register of the Altera SPI Core is made by mask with positive logic:
CS definitions from platform_drivers.h are:
#define AD9528_CHIP_SELECT 2#define AD9371_CHIP_SELECT 1
And this is right because of pin assignments on board.
Right selection of master CS is:
IOWR_32DIRECT (SPI_BASEADDR, ALT_AVL_SPI_SLAVE_SEL_REG, dev-> chip_select);
Now I go futher and get next error:
device-> rx-> rxAgcCtrl-> agcGainUpdateTime_us out of range in MYKONOS_setupRxAgc ()
Hope, it will not take much time to debug ...
The project was not yet updated according to the latest HDL changes on 2017_R1 branch. We will do this and let you know when it's ready.