Error in FPGA design of ADRV9371 for A10GX

Hello.

 

Now, I go thru building and checking AD FPGA AD9371 project on my development kits Arria 10 GX and ADRV9371-W / PCBZ.

 

My current configuration is:

 

Project: hdl \ projects \ adrv9371x \ a10gx

Project brunch: Master

Nios project: no-OS \ ad9371 \ sw \

NIOS branch: 2016_R2

Quartus Prime: 16.0.2.222 standard edition

Eclipse (comes with quartus): Kepler Service Release 2 Build id: 20140224-0627

 

I spent 2 days to debug the following error, which I found in platform_drivers.c downloaded from Git.

 

The symptom is: when NIOS wrote SPI configuration words to AD9528, they really get to AD9371. The reading is doing the same from AD9371. And vice versa.

The cause is: Wrong selection of CS signal in platform_drivers.c:

 

IOWR_32DIRECT (SPI_BASEADDR, ALT_AVL_SPI_SLAVE_SEL_REG, ~ (dev-> chip_select));

 

Here, no need to inverse (dev-> chip_select), because selection of active masters in slaveselect register of the Altera SPI Core is made by mask with positive logic:

https://www.altera.com/documentation/sfo1400787952932.html#iga1405558422226

CS definitions from platform_drivers.h are:

#define AD9528_CHIP_SELECT    2
#define AD9371_CHIP_SELECT    1

And this is right because of pin assignments on board.

 

Right selection of master CS is:

IOWR_32DIRECT (SPI_BASEADDR, ALT_AVL_SPI_SLAVE_SEL_REG, dev-> chip_select);

 

P.S.

Now I go futher and get next error:

device-> rx-> rxAgcCtrl-> agcGainUpdateTime_us out of range in MYKONOS_setupRxAgc ()

Hope, it will not take much time to debug ...

  • MCS successful
    CLKPLL locked
    AD9371 ARM version 5.1.1
    PLLs locked
    Calibrations completed successfully
    ATX PLL calibration OK
    ch 0 TX termination and VOD calib OK
    ch 1 TX termination and VOD calib OK
    ch 2 TX termination and VOD calib OK
    ch 3 TX termination and VOD calib OK
    ch 0 CDR/CMU PLL & RX offset calib OK
    ch 1 CDR/CMU PLL & RX offset calib OK
    ch 0 CDR/CMU PLL & RX offset calib OK
    ch 1 CDR/CMU PLL & RX offset calib OK
    RX_XCVR initialization OK
    TX_XCVR initialization OK
    RX_OS_XCVR initialization OK
    RxFramerStatus = 0x20
    OrxFramerStatus = 0x20
    DeframerStatus = 0x21
    dac_setup dac core initialized (122 MHz).
    adc_setup adc core initialized (123 MHz).

    Done

    Yep! It was a little hard to run all this things...

    device-> rx-> rxAgcCtrl-> agcGainUpdateTime_us out of range in MYKONOS_setupRxAgc ()

    It was because AD9371 Tranciver Evaluation Sofware save  in c-profile agcGainUpdateTime parameter as 0, until I've updated AGC Rx chanell parametrs by pushing button.

  • 0
    •  Analog Employees 
    on Dec 27, 2017 9:50 AM

    Most people are out, and we will get back to you in early Jan.

  • 0
    •  Analog Employees 
    on Jan 18, 2018 8:13 AM

    Hi,

    The project was not yet updated according to the latest HDL changes on 2017_R1 branch. We will do this and let you know when it's ready.

    Thanks,

    Dragos

  • Hi
    I returned to work with this project after a pause. As I understand, last time, I'd got JESD synchronization error:
    ....
    RX_XCVR initialization OK
    TX_XCVR initialization OK
    RX_OS_XCVR initialization OK
    RxFramerStatus = 0x20
    OrxFramerStatus = 0x20
    DeframerStatus = 0x21
    ....
    Could it be result of not updated project on your Git repository?
    Will you plan to update master branch of hdl and no-os driver with new A10GX supported project?

    My current configuration is:
    Project: hdl\projects\adrv9371x\a10gx\
    Altera project brunch: Master
    No-OS project brunch: 2016_R2
    Quartus Prime: 16.0.0 build 211 standart edition
    Eclipse (comes with quartus): Version: Kepler Service Release 2 Build id: 20140224-0627

  • 0
    •  Analog Employees 
    on Feb 15, 2018 2:11 PM

    Hi,

    Sorry for the delay. We just committed some changes to the no-OS master branch - they were not yet fully tested but you can have a look.

    Dragos