How to fix communication with AD9121 based on FMCOMMS1 Reference Design?

I’m using the AD9121-M5372-EBZ evaluation board connected by FMC with a ZedBoard. First of all I modify HDL reference design (ADFMCOMMS1) by deleting the ADC IP blocks from block design and change pinout on FMC Connector. The differences between both evaluation boards (AD9121 and FMCOMMS1) are mainly in connection number in FMC connector. I only want to send data samples from Linux to AD9121.

Some help including editing DTS and drivers were described in this post: AD9121-M5372-EBZ based on AD-FMCOMMS1-EBZ .

 

It seems that on the I/Q outputs of the AD9121 evaluation board there is some data, and after I made some changes in code it changing the output, but unfortunately I can't force DAC to get reasonable data e.g. the square/sawtooth wave. The 500 MHz reference clock is supplied to the DAC. I have set the options from PC:

PLL is indicating as locked. However when registers are read from the DAC, there is some Warning 1 and Warning 2 of FIFO appearing - I think its the result of my problem.

I have checked almost everything in project:

- FGPA (especially the pin mapping and DMA addressing),

- the clocking signals (I checked that DCI/DACCLK signals are synchronized and seems that they are ok).

But when I checked the signals in FMC connector lines it seems that they are not working properly when the signal is changing through time (only first two bits seems working properly when I implemented simple counter).

However, they have correct states when I put static values into the buffer (e.g. buffer of 1024 samples, all of them are 0x01 or 0x02 etc.) - that proves that pins maping is correct in HDL project.

Do someone have any idea where the problems is?

  • 0
    •  Analog Employees 
    on Feb 12, 2018 1:04 PM

    I opened up a new thread in the High-speed DAC community, hopefully, somebody there can help us out with a schematic. AD9121-M5372-EBZ schematic 

    It looks like a pin mapping issue to me, maybe there are more differences between the two boards...

  • 0
    •  Analog Employees 
    on Feb 12, 2018 2:36 PM

    The core is using SERDES macros to decrease the clock rate of the interface. The dac_clk will be 1:4 of the DCI frequency and the data lines will contain 4 consecutive samples for each channel.

    Did you update the input clock period of the MMCM? hdl/axi_ad9122.v at master · analogdevicesinc/hdl · GitHub This can be an issue. By default, the core is tuned to a 600 MHz DCO. You can check if the MMCM is locked by reading the dac_status register of the register map. (0x405C) 

  • Hello,

    Thank You for reply.

    If I understand you correctly you're using the axi_ad9122 core to interface this device.

    Yes.

    What happens if you simply generating a tone with the build in DDS?

    I am now trying to put some sawtooth module as an input data of axi_ad9122 core. Is that what You mean?

    The ad9121 has 14-bit resolution, how did you modify the core?

    I didn't at all. I just assumed that first two bits are ignored on the output pinout and when I fill the buffer with the data I ommit the first two bits (just shift).

  • If I understood you correctly I should build "No-OS" project and use the functions that You provide from the driver? I am asking for clarification because I haven't used the "No-OS" solution.

    Another question is can You share the electrical schematic to board AD9121-M5372-EBZ? There is no such files in the internet, only to the AD9122 evaluation boards.

  • If you're using Linux, and the system probes the core, by default DDS should be started. So if you have a valid DCI/DCO from the device, you should see some movements on the data lines.

    Yes, I am using the Linux and the system probes the core so by default DDS is starting. Below You can see the data on the IQ output: 1. DAC1_P, 2. DAC1_N, 3. DAC2_N, 4. DAC2_P. I have measure that the DCI signals have 125 MHz frequency.

    After I made some changes in code it changing the output, but unfortunately I can't force DAC to get reasonable data e.g. the square/sawtooth wave. Thats my problem.