I am wondering if anyone can help me regarding the AD JESD204b RX core developed by Analog Devices
1. AXI JESD204 RX core
JESD204B Link Receive Peripheral [Analog Devices Wiki]
The above link describes the AD AXI JESD204b Rx core. However, when I downloaded the source code, the verilog HDL code does not have the data in/out interface as following. There is NO RX_PHY ports and RX_DATA ports in the axi_jesd204_rx.v file. The lack of I/O interface can bee seen in the below link as well
. hdl/axi_jesd204_rx.v at dev · analogdevicesinc/hdl · GitHub
I am wondering how can we use this core if it does not have input/output interface.
2. NON-AXI JESD204 RX core:
I also downloaded the non-AXI AD JESD20b core. I tested this core and found that it does not support the character alignment insertion function (FACI). Even thought it has scrambler module, but when I tested the JESD link with scrambler enabled, it failed. In summary, this non-axi core only works when the scrambling and FACI are disabled.
What are your thoughts about this?
1. The referenced documentation refers to the block that is created by the adi_jesd204_rx_create function. It is a combination of the two cores you mentioned, one core for the register map and one for the JESD204 protocol handling.
2. Character replacement is not supported when scrambling is disabled. Scrambling itself is supported though, and character replacement is supported when scrambling is enabled. For link performance reasons we highly recommend to always enable scrambling.
Which component are you trying to interface the core to where you were experiencing issue with scrambling enabled?
Thank you very much for your reply.
1. Now I understood the the axi_jesd_rx.v only provides the register map functionality, not the the protocol handling.
2. The rx.v implements the protocol and its configuration is done thru either the axi_jesd_rx. v or rx_static_config.v. Actually, I have used rx_static_config.v so far.
3. I am NOW able to get the scambling test work. My test involves AD9208_300EBZ as Tx and the Xilinx VCU118 as Rx.
4. Regarding the character replacement feature of AD JESD Rx core. I am wondering where this function is actually implemented. Because I could not be able to find the implementation of this feature in the rx.v file (hdl/library/jesd204/jesd204_rx). The jesd204_rx module of this file has an input port named cfg_disablle_character_replacement. But this input is not connected to any logic inside the module. I am not if I am missing something here. Can you please help me with this issue?
5. As part of my effort to debug the character replacement, I tried to run the script called jesd204.tcl which is located at script hdl/library/jesd204/scripts. However, I came up with an error called invalid command name "ad_ip_instance". I guess the error occurred because the ad_ip_instance's definition is not found anywhere. Can you please help me a proper way to run the jesd204.tcl script?
Thank you very much for your help.
4. You are right the cfg_disable_character_replacement is not used. It is only used for the TX interface. When scrambling is enabled during character replacement D28.7 gets replaced with K28.7. The only difference between the two is the char_is_k value.
5. The adi_ip.tcl script has all the helper commands.
1. Replacement is implicit, the binary values of the replaced and non-replaced character are identical.
I hope you understand that we can not provide a detailed line by line explanation of source. We provide the JESD204 link layer transmit and receive peripherals as a component with a well defined external interface. We can answer questions about how to work with those interfaces and their behavior. But we cannot provide detailed explanations of the internals of the peripherals.
2. Both option a) and option b) are supported. The peripheral is JESD204 Subclass 1 compatible.
Thank you so much for your reply.
Unfortunately, I am still quite confused.
1. First, I look at the HDL files under hdl/library/jes204b and still can not see where the D28.7 to K28.7 replacement occurs. In the rx_lane.v file, I can see the the charisk28[i] is asserted when char[i][4:0] ='d28 and phy_charisk[i] = 1
if (char[i][4:0] == 'd28 && phy_charisk[i] && char_is_valid[i]) begin
charisk28[i] <= 1'b1;
But after this point, where does the replacement happens?
I have closely looked into all the codes in rx_lane.v but can not find that logic implementation.
Can you please help me with this?
2. Second, In the JESD204b standard (July 2011 Version), section 18.104.22.168.3 on page 61 (Character replacement with scrambling), it mentions 2 cases:
a. Two sides support lane synchronization: two control characters are used. At TX, if the last octet of frame is 0xFC, it is replaced by /F/ or K28.7. And if the last octet of a multi frame is 0x7C, it is replaced by /A/ or K28.3
b. At least one side does not support lane synchronization: At Tx, if the last octet of the current frame is D28.7, then it is replaced by K28.7
So, my understanding is that the AD JESD RX core only implements option b. Am I correct?
If that is the case, according to the JESD204b section that I just mentioned, option b corresponds to NMCDA-SL which stands for No Multiple Converter Device Alignment, Single Lane. Does this mean that we can not use this core if the Tx and Rx operates in Subclass 1. In my design, I am using AD9208-3000EBZ and I need to operate it in subclass 1. Is my understanding correct, Lars?
Thank you very for being patient to me.