Hi guys,
I need help configuring the clocks from axi_ad9361.
I need to decimate data from ADC from 40msps to 2msps. I’m using Xilinx FIR compiler to decimate.
My partners told me that axi_ad9361’s I_clk runs at 4* sampling rate?
so in my case it’d be 160 MHz.
My partner also told me that adc_i0_valid come out at same clocks rate as sampling rate? so 40 MHz for my case
so what I Did was add a clock inverter for the adc_i0_valid and used the inverted signal for the clock of my FIR compiler. Furthermore, I added a 2Mhz clock fabric PL clock ( don’t know whether to use IOPLL or DPPLL) and made a custom module to latch the data from FIR filter to the 2 MHz then proceed to my processing.
is there anything wrong with the order of operations above?
im using Linux do I need to edit device tree for this new 2Mhz clock?
i can really use some help on this.
