I am working subclass-1 concept. I've few doubts which are quite complex :
1) I am seeing my lane latency is keep on changing b/w "1Multiframe and 49 Octet" To "1Multiframe 62 Octet" on each power-up.
Does it means that there is no deterministic latency ?
2) How can we calculate LMFC_OFFSET for framer and deframer ?
3) Do we need to set same LMFC_OFFSET value in FPGA which we are using in AD9371 ?
4) How can we calculate RBD value ?