Build Zynq boot Image with debug probes


I have a custom HDL design for timed transmissions on ADRV9361z7035. I have some ILAs in different places to check the signals of my custom IP. After the synthesis and bitstream generation, Vivado gives me an .ltx file in addition to the .hdf file which is needed for building Zynq boot image according to I use the script here:

How can I integrate the debugging probe file (.ltx) into the boot image?

I want to check ILA datas over JTAG.

Thank you for your help in advance,


  • +1
    •  Analog Employees 
    on May 7, 2020 12:43 PM


    You don't need the .ltx. Generate the BOOT.BIN, use it to boot the system and you should be good to go.
    If your ILA is not showing it might be a clock problem.
    Let me know if you have any issues whit it.


  • Hey Andrei, I might be in a similar position. Our team currently uses a petalinux makefile build process to generate the boot.bin for the FPGA. When I boot up the FPGA after that process has finished, I don't see the actual ILA probes populating in Vivado's Hardware Manager. I see the ILA instances, but not the probes. Vivado tells me to 'Specify the probes file and refresh the device'. Refreshing alone does nothing, but if I re-program the device, I can see all of the ILA probes correctly. The only problem here, is that the FPGA no longer behaves correctly, since I think the petalinux build process incorporates more than just my bitstream. So I'm kind of stuck, either I use the existing petalinux build process and I can't see my probes, or I program the FPGA in Vivado, but the FPGA doesn't seem to work correctly. Any other ideas as to what could be the problem?

  • 0
    •  Analog Employees 
    on Mar 25, 2021 11:40 AM in reply to citizenkoehn

    How are you building the HDL? GUI or make?


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