Hi,
I need a clock in the ADRV9009/ZCU102 reference design that is 4x faster than the clock generated by axi_adrv9009_rx_clkgen. The clock generated by axi_adrv9009_rx_clkgen will be 61.44MHz so I need to generate a 245.76MHz clock.
I was planning to use the AXI_CLKGEN IP block. The clk input to this block will be the same as the clk input to axi_adrv9009_rx_clkgen. I have a couple of questions;
1) Is this the best approach to generate the 245.76MHz clock.
2) What settings should I use to customise the IP block prior to sythesis/implementation?
3) Do I need to do any further configuration via the AXI interface when the design is running on the FPGA?
Thanks
