ADRV9009 ORX at 491.52 Msps


I would like to know how the timing looks like for the ORX data of a ADRV9009 at 491,52 MHz sampling rate. I understand that both ORX channels are bundled in this mode.

A quick look with Xilinx ILA, clocked with axi_adrv9009_rx_os_clkgen/clk_0, at the adc_data_* output lines of rc_os_adrv9009_tpl_core shows new data at each data line for each clock cycle. That would mean, that the clock is still at 245,76 MHz for 491,52 Msps mode. Is this correct?

The only remaining question then would be, which data values correspond to earlier points in time - data_0/data_1 or data_2/data_3.

Thank you, and best regards,


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  • Hmm. As I understood, in 491.52 MSPS mode all 4 ADCs of the ORX are used for stitching.

    I guess this will not work if RX_OS_NUM_OF_CONVERTERS is set to 2, will it?

    Best regards,


    BTW, the rearrangement of the ORX data to true 491.52 MSPS now works for me. Even the DMA seems to be happy with the double clock frequency.

  • 0
    •  Analog Employees 
    on Mar 19, 2020 1:45 PM over 1 year ago in reply to EHeinz689

    I need to test in hardware the exact configuration, but to my understanding even though all 4 ADCs are used, from the JESD204 perspective the data will be arranged as if there are only 2 converters, corresponding to I/Q, it's just that you're merging the data manually not in an unified transport layer.

    If your setup is working as is, it's probably better to continue with it.