I would like to know how the timing looks like for the ORX data of a ADRV9009 at 491,52 MHz sampling rate. I understand that both ORX channels are bundled in this mode.
A quick look with Xilinx ILA, clocked with axi_adrv9009_rx_os_clkgen/clk_0, at the adc_data_* output lines of rc_os_adrv9009_tpl_core shows new data at each data line for each clock cycle. That would mean, that the clock is still at 245,76 MHz for 491,52 Msps mode. Is this correct?
The only remaining question then would be, which data values correspond to earlier points in time - data_0/data_1 or data_2/data_3.
Thank you, and best regards,