I am using the AD-FMCDAQ2-EBZ with the Xilinx ZC706 SoC for data acquisition and digital processing. I am integrating my design into the provided HDL reference design, using the hdl_2018_r2 branch of the daq2 hdl reference design. The reference design uses a native sampling rate on the ADC (ad9680) of 1 GSPS which I am changing to 400 MSPS and then using one of the digital down converters on the ad9680 get an effective sample rate of 200 MSPS. My question is: if I change the sampling rate used in the reference design by modifying the registers in the ADC, how do I change the data rate used in the rest of the HDL pipeline? Currently, since the sample rate is 1 GSPS, the quad-parallel data is appearing in the reference design IP cores at 250 MHz. I will be changing the effective sample rate to 200 MHz, so I need the quad-parallel data rate to be 50 MHz within the HDL reference design. What are the steps necessary to accomplish this?
I am basically just wondering if I need to change the data/clock rate for all of the involved IP's? or if there is an automated way to propagate this change throughout the reference design.
Hi,To change the sample rate you have to use the software.What software are you using? Linux or no-OS.Basically you have to reduce the JESD link rate. This means chancing parameters for the clock device, adc device and fpga.To have an overall idea on the system configuration, you can take a look on the no-OS code(base config). Andrei
I am using the Analog Devices Linux, not no-OS. Will the software that I need to modify be in a significantly different place? I will have to set things up differently in device-tree and other ingredients before compiling the entire system, correct?
If I am using the ADI linux, I can change these parameters for the clock device (ad9523), adc devices (ad9680), and fpga by modifying the devices tree source file (.dtsi) before it is compiled to the platform-specific device tree file (.dtb) correct?
That should suffice in case the rates of the JESD lanes and the VCO of the PLL are within the FPGA/AD9680 range. Otherwise, you may need to recompile the HDL design also.