Pipeline Data Rate AD-FMCDAQ2-EBZ

I am using the AD-FMCDAQ2-EBZ with the Xilinx ZC706 SoC for data acquisition and digital processing. I am integrating my design into the provided HDL reference design, using the hdl_2018_r2 branch of the daq2 hdl reference design. The reference design uses a native sampling rate on the ADC (ad9680) of 1 GSPS which I am changing to 400 MSPS and then using one of the digital down converters on the ad9680 get an effective sample rate of 200 MSPS. My question is: if I change the sampling rate used in the reference design by modifying the registers in the ADC, how do I change the data rate used in the rest of the HDL pipeline? Currently, since the sample rate is 1 GSPS, the quad-parallel data is appearing in the reference design IP cores at 250 MHz. I will be changing the effective sample rate to 200 MHz, so I need the quad-parallel data rate to be 50 MHz within the HDL reference design. What are the steps necessary to accomplish this?