I've been studying the FMCOMMS2 Zed project included in the analog devices github repository. I'm working on several AXI Streaming IP Cores for my master's project and would like to interface them between the util_cpack2 and ADI AXI DMA Controller. I'd prefer not to write more code than I have too. Is there any existing IP core to convert the FIFO out of util_cpack2 to an AXI Stream? Has anyone modified the util_cpack2 core to use a AXI Stream instead? 

I see that the ADI AXI DMA Controller can do this but was trying to also avoid two DMA Controllers to keep latency low.

Can the DMA Controller be configured as a dumb core that just converts the FIFO to AXI Stream?

I'd like to retain the use of IIO Scope and GNU Radio as much as possible.

On the DAC side there is a AXI Streaming Master to the util_upack2 that I can directly insert my cores easily.

Thank you in advance for any guidance.

  • 0
    •  Analog Employees 
    on Feb 20, 2020 11:46 AM 8 months ago

    Moving to FPGA subspace.

  • 0
    •  Analog Employees 
    on Feb 21, 2020 11:59 AM 8 months ago

    You can connect the FIFO interface directly to an AXI Stream. In the case of the cpack2 module, the connection would be:

     - packed_fifo_wr_en   -    s_axis_valid

    - packed_fifo_wr_data -    s_axis_data

    - packed_fifo_wr_overflow -- should be treated separately; will be asserted if the s_axis_ready is not asserted at a valid data (there is no backpressure in case of FIFO, the slave must be always ready during a transaction)

    - packed_fifo_wr_sync -- should be treated separately; it indicates whether the first enabled channel is in the first output sample


  • I came across post on some other site that said it could be directly connected but did not give any details. 

    No backpressure is fine, my cores will all be able to complete before the next samples are ready. As for the packed_fifo_wr_sync, it looks like it will always be true since there are 4 channels and all are packed into the packed_fifo_data signal at once as per the notes in pack_shell.v. 

    Looks like i should probably setup a sim to verify connectivity and operation.

    Thank you for the help! 

  • I was able to make a core that translated the signals. I split the 64bit wide fifo into two 32bit Streams as noted above with the inversion of the overflow signal. I can now drive my AXI Streams from this core. Thank you for the help! The core is limited but functions for me needs. I can post the code if anyone else might find it useful.