Zynq7045 Supporting 3 AD9361s simultaneously

I am curious if the Zynq 7045 can support up to 3 AD9361's at the same time (LVDS mode). I am assuming the following requirements must be met...

  • Each AD9361 on its own HR Bank to support the reference clock to a regional clock pin
  • Each AD9361 needs its own instantiation of the AD9361 IP Core
  • Each AD9361 can share a SPI bus using appropriate CS logic
  • Each AD9361 must have independent reset lines

Anything I am missing? Is there a blatant reason this would not be supported? Has anyone tried this before?

can have -> must have independent resets
[edited by: jgutel at 11:17 PM (GMT 0) on 17 Feb 2020]