I am curious if the Zynq 7045 can support up to 3 AD9361's at the same time (LVDS mode). I am assuming the following requirements must be met...
Anything I am missing? Is there a blatant reason this would not be supported? Has anyone tried this before?
It should support multiple AD9361. Fmcomms5 is an example on how to support 2 (https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms5)
Not sure about needing its own HR bank, but the rx interface (data,frame,clock) should be on the same bank and the clock should come in through a clock capable pin. For the TX side, all the pins of the interface should be on the same bank, but TX clock doesn't need to be on a clock capable pin.
Each AD9361 needs it's own IP core, can be connected to the same SPI with different CS and would be best to have independent reset line.
If you need to synchronize the AD9361s, please look over: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync