PlutoSDR HDL issue


I'm trying to add a custom signal generator module to the PlutoSDR (TX only). The blocks are working on an FMCOMMS2-based design but exhibit a strange artifact on the Pluto.

- All DMA blocks have been removed, the interpolator and decimator blocks have been removed, the RX path has been bypassed in the HDL configuration to save space in the device. 1R1T mode is selected as in the "factory" Pluto design.

- The AD936x HDL block is driven by a CDC FIFO, which is fed by my custom signal generator IP (running off FCLK0 of the FPGA). The 32 bit data is split to 16 bit channels and go to dac_data_i0 and dac_data_q0, respectively. dac_data_x1 are tied to GND. on its output side the CDC FIFO is being clocked by l_clk (rd_clk == l_clk), and rd_en is tied to dac_valid_i0.

My problem is that there seemingly happens an unwanted zero stuffing somewhere. When I'm running the internal PRBS, the output spectrum reflects the desired filter shape. However, when I switch to my generator, the resulting spectrum is compressed by a factor of two, and repeats twice (the second replica gets partly filtered of course by the filters in the AD9361). I.e., if I needed to see two discrete peaks 100 kHz apart, they now appear 50 kHz apart and the entire spectrum repeats itself once more.

ILA'ing the FIFO output shows that rd_en (dac_valid_i0) is high every other clock (I think). I also think the FIFO correctly produces new data on every valid period, and does not change otherwise (see screenshot). 

've attached some screenshots. Please help me to identify the issue.

Best regards,