I'm trying to add a custom signal generator module to the PlutoSDR (TX only). The blocks are working on an FMCOMMS2-based design but exhibit a strange artifact on the Pluto.
- All DMA blocks have been removed, the interpolator and decimator blocks have been removed, the RX path has been bypassed in the HDL configuration to save space in the device. 1R1T mode is selected as in the "factory" Pluto design.
- The AD936x HDL block is driven by a CDC FIFO, which is fed by my custom signal generator IP (running off FCLK0 of the FPGA). The 32 bit data is split to 16 bit channels and go to dac_data_i0 and dac_data_q0, respectively. dac_data_x1 are tied to GND. on its output side the CDC FIFO is being clocked by l_clk (rd_clk == l_clk), and rd_en is tied to dac_valid_i0.
My problem is that there seemingly happens an unwanted zero stuffing somewhere. When I'm running the internal PRBS, the output spectrum reflects the desired filter shape. However, when I switch to my generator, the resulting spectrum is compressed by a factor of two, and repeats twice (the second replica gets partly filtered of course by the filters in the AD9361). I.e., if I needed to see two discrete peaks 100 kHz apart, they now appear 50 kHz apart and the entire spectrum repeats itself once more.
ILA'ing the FIFO output shows that rd_en (dac_valid_i0) is high every other clock (I think). I also think the FIFO correctly produces new data on every valid period, and does not change otherwise (see screenshot).
've attached some screenshots. Please help me to identify the issue.
In the all AD9361 design, the data streams (both input and output) are controlled by the device (AD9361) itself, through its digital interface. To put this in your context, all your data should be validated using the dac_valid signals generated by the axi_ad9361 core. You're are doing something with the dac_valid signal, but don't know exactly what.
Also, I highly recommend writing a simple test bench, where you can validate your custom data path.
thanks for the quick reply. Maybe the figures and hier blocks have obscured details of the HDL design, let me try to explain it better:
- I have done a testbench and it produces the correct output (spectrum). This design is really stripped down to the barest basics, I'm wrestling with this ghost image for many days now.
- I have attached a picture to my original post that I had obtained using the ILA. This confirms, at least to me, that once the CDC FIFO's rd_en (first line) goes high, dout changes. It changes on every edge, and on the edges only. In fact, the dout values seen in the figure correspond exactly to the time domain samples that I fill into the write side of the CDC FIFO, no missing samples or other weird stuff. (The numerical sample sequence at the read output of the FIFO is exactly what I expect). The rd_en signal is directly driven by dac_valid_i0 (let me attach a more complete screenshot where this is clearly seen). I would think the data that I feed to axi_ad9361 corresponds to the expected format. Here again: first line: dac_valid_i0, second line goes to the DAC sample inputs via slicers.
Here is the relevant part of the block design. tx_postproc is a trivial block that does nothing ATM, only converts the AXI stream to the FIFO protocol.
I'm not sure where else to look. I think this has to do with unwanted sample rate change of 2 somewhere. The filter I'm using (a bit too tight but hey) is as follows:
I did verify the reported sample rate (it is indeed 6.144 MHz), FIR filters are enabled according to the driver, etc.
The test program configures the DAC data channels like so:
I can not see anything strange, unfortunately. Can you check the parallel port configuration of the device? (registers 0x010, 0x011 and 0x012) You can find more info about these registers in UG-671.
reg 16: 0xc8 (PP TX Swap IQ, PP RX Swap IQ, RX frame pulse mode)
reg 17: 0x00
reg 18: 0x42 (Swap ports, Full port)
Seemingly identical to the values in the stock pluto.
Hi,Can you do a test with the internal DDS(axi_ad9361)? This is to validate the Tx path.At what rate do you generate your data(FCLK0)?