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AD9371 Recommended for New Designs
The AD9371 is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal...
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Zynq3-AD9371 Radar



		

			

									
					    jsprick
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jan 20, 2020 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    I'm wanting to implement a zynq3-AD9371 combo as a radar system. I want to be able to decide when each iteration of the waveform in memory is transmitted and when they are received/recorded. I'm also wanting to just record snippets of the received data in memory rather than streaming it. Before, I get started, I'm wondering where in the HDL might be the best place to start injecting my code. Also, I had already asked elsewhere, but are there any alternatives?
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
			                            
                        
                on Jan 22, 2020 1:49 AM
            
            
					
      
	
      

		
		
      
					
      To synchronize TX and RX requires several changes to the HDL reference design as well as some understanding of the DMA itself. Also, when we say synchronized I mean that when data leaves the DMA on the TX side it starts allowing data into the DMA on the RX side. The delay from TX to RX should be consistent for a given profile, but you will have to measure it.
      

      These are the changes I would make to create synchronized captures:
      

      1. Remove tx clock generation and connect the tx path to the rx path clocks. This should allow you to connect the ADC and DAC DMAs together.
      

      2. You will need to hook up the output valid of the DAC DMA to the ADC DMA input valid. On other designs, users would typically put some logic here to delay or latch this valid signal into the ADC DMA to have finer control. With these connections when a DAC DMA transfer is performed the ADC DMA will start to collect data.
      

      In software, you will have to program the ADC DMA to be ready to accept new data. This is usually done by simply creating a buffer in libiio. Then once you submit a buffer to the DAC DMA, the ADC DMA will start to fill. Once the ADC DMA is filled you can pull the buffer from software, which will be the synchronized data.
      

      -Travis
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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