I am working with the ADRV9361-Z7035 boards with the reference design from Analog Devices. I use only one channel RX1A and only in receiving mode to do a very simple LTE cell search. The UE (which is an ADRV board) should detect and decode the synchronization sequence on 2.68 GHz frequency with the sampling rate of 1.92 MHz.
Since I am using srsLTE here, the ADRV board only samples the RX channel with the rate of 1.92 MHz and sends I/Q data to the host for decoding over Ethernet. Hence, no serious signal processing is being done on the FPGA. It is only transferring the samples to the LibIIO and then through the LAN to the host.
Here is the problem:
Only when I put a very big fan on top of the z7035, decoding is successful. Even the fan you mentioned in one of the other questions is not sufficient: FHP27-27-20/T710/M I bought it and installed it on the FPGA but it doesn't help (The fan power pins on the FMC are placed incorrectly and the fan does not turn on, so I had to modify the socket of the fan!).
I think the ARM on the FPGA drops the samples due to overheating. I can say that when the FAN is on, the decoding works and otherwise it doesn't.
If it works with the big fan then what is the problem:
Even with the big fan, my problem is still there because the UE switches to the 5.72 MHz and the decoding is not successful at all in this sampling frequency.
I would be grateful if you help me with this overheating issue.