What clocks are available in the ADRV9009/ZCU102 FPGA reference design?
I am using a sample rate of 61.44MSPS, so adrv9009_rx_device_clk is 61.44MHz and adrv9009_tx_device_clk is 30.72MHz.
Are there any clocks > 200MHz that are synchronous to the 61.44MHz and 30.72MHz clocks? If so, what are there called in the reference design?
There are no clocks 200MHz+ that are synchronous to the device clocks.