AD-FMCDAQ2-EBZ axi_ad9680_core IP core documentation

I am working on a project which is built on the AD-FMCDAQ2-EBZ reference design branch hdl_2018_r2 running on the Xilinx zc706 evaluation board. The reference design contains analog devices IP core "axi_ad9680_core," while I understand generally how this IP core works, I am trying to find any relevant documentation that will tell me the data format used by the core. I need to know the endianness and any padding of the 14-bit ADC samples when configured with 4-lanes of JESD204. I know that the two 64-bit channels are each comprised of 4 ADC samples, but I do not know the exact format of how the data is packaged.