I am working on a project which is built on the AD-FMCDAQ2-EBZ reference design branch hdl_2018_r2 running on the Xilinx zc706 evaluation board. The reference design contains analog devices IP core "axi_ad9680_core," while I understand generally how this IP core works, I am trying to find any relevant documentation that will tell me the data format used by the core. I need to know the endianness and any padding of the 14-bit ADC samples when configured with 4-lanes of JESD204. I know that the two 64-bit channels are each comprised of 4 ADC samples, but I do not know the exact format of how the data is packaged.
Hi,The axi_ad9680 will be replaced with the ad_ip_jesd2014_tpl_adc IP. using the same data format.
Please look at https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc.
These links might also be helpful:
"Will be replaced" as in is currently replaced in the 2019 reference design? I am trying to figure out which version of the HDL repository to use. I am currently using the 2018r2 version of the reference design, and need somehow send a custom generated signal out through the ad9144 and receive it on the ad9680 where it can be re-routed into a custom filter I have developed in Xilinx system generator and imported as an IP product with Xilinx IP integrator in Vivado. Should I update to the most recent version of the HDL repository to use the ad_ip_jesd204_tpl_adc IP instead of the ad_9680_core?
Do you recommend integrating the new ad_ip_jesd204_tpl_adc/dac IP into one of the existing reference designs to replace the ad_9680_core and ad_9144_cores? Or is there a current branch of the ad-fmcdaq2-ebz HDL reference design that already contains these upgrades?
Am I correct that the ad-fmcdaq2-ebz always transmits sampled data from the ad9680 as in-phase and quadrature-phase components? I read a contradictory thread that said that the two 64-bit data streams coming into the ad_9680 core correspond to two sets of four consecutive real-valued samples since the ad9680 is a "dual" adc and has two channels.
Hi,I recommend using the hdl_2019_r1, as it has more features than the old version. For now the generic TPL cores are wrapped in the ad9144 same for ad9680. In the future we plan to remove the ad9144 and ad9680 altogether and use only the generic JESD TPLs. There is no exact timeline for this. If you want to do the replacement yourself is up to you and your needs for different configurations.Take dac_fmc_ebz project for example, it supports multiple boards and configurations.https://github.com/analogdevicesinc/hdl/blob/master/projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl#L67But I don't think generating hdl for multiple operating modes is what you are looking for.
GriffinBonner said:Am I correct that the ad-fmcdaq2-ebz always transmits sampled data from the ad9680 as in-phase and quadrature-phase components?
There is a DDS in the DAC TPL(ad9144) that is made for this. You can very easily play with it from the IIO-Oscilloscope if you run Linux on the board.
GriffinBonner said:I read a contradictory thread that said that the two 64-bit data streams coming into the ad_9680 core correspond to two sets of four consecutive real-valued samples since the ad9680 is a "dual" adc and has two channels.
That is the default configuration of the system.