ad9361 data clock division w/o fifo


I've been looking into the implementation of the util_clkdiv and then stumbled over this discussion on the xilinx forums. In short, it's exact;y about how you can safely divide a "fast" clock by some integer value to get a "slower" one.

The discussion stated that when using BUFR after BUFG (what is seen in the ad9361 reference design) you'll get mesochronous clocks and need to use FIFO's for the datapath.

However, if you use a BUFG in pair with BUFGCE (as on the diagram), then you get synchronous clocks and don't have to worry about synchronization anymore. 

It seems like an easy patch for the reference design to remove util_clkidiv IP and change ad_data_clk.v to include the above diagram. But maybe I am missing something and this won't work at all?

P.S. By no means I am proposing these changes into the mainline repo. This is an experiment I would like to conduct for my own design.

Best regards,