This question is only related to AD9361 HDL design vs specific Ultrascale board. DDR, pinouts, routing, timing, etc in relation to the carrier board is not what I am concerned at the moment.
I am planning a project to port the existing AD9361 HDL reference design to TRENZ Ultrascale xczu4cg FPGA (https://shop.trenz-electronic.de/en/TE0803-03-4AE11-A-MPSoC-Module-with-Xilinx-Zynq-UltraScale-ZU4CG-1E-2-GByte-DDR4-5.2-x-7.6-cm?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0803/REV01).
For planning purposes I need to understand if there is any show stopper that I should consider here? Or if there are no big alarms how about the I and O SERDES? Does zcu102 design have everything I need? Is there anything I need to modify in that AD9361 core? I didnt fully understand how is SERDES really used in the AD9361 design but I noticed that ISERDES2 (instead of 3) is used in /xilinx/xommon/ad_serdes_in.v but that doesnt seem to be instatinated anywhere (or I didnt see it).
I have seen several threads on this forum for similar topic but nothing is really answering what I am after? I read the porting doc https://wiki.analog.com/resources/fpga/docs/hdl/porting_project_quick_start_guide.
Any comments will be much appreciated. Many thanks,
The ad9361 does not use SERDES macros. Look at xilinx/common's ad_data_in.v, ad_data_out.v, and ad_data_clk.v to see what macros are used in the low level. As you will see we're using simple IO buffer and IO delay controllers.
What is your targeted interface type, CMOS or LVDS? You should not have any big show stopper.
Thanks Istvan for the reply. Much appreciated.
Very nice! Understood! Good to know.
The interface type is LVDS. So hopefully it all should be ok (will know in couple of weeks when I get to it :)).