I want to move my zynq7 design with a AD9122 to zynq ultrascale+. I already recognized, that there is only oserdese2 available and changed that to oserdese3. What else do I need to do? I have also the problem, that I cannot read from the version register of that axi_ad9122 core other cores working fine. But on that i read only 0xdeaddead.
From what HDL have you started the port ?
Are you using a ZCU102 or a custom FPGA Carrier ?
I am now on the master branch and I am using a enclustra xu5 module with a zu4ev SoC on a custom board with the AD9122. On the zynq7 design it works fine with 2015.4 release and a enclustra zx5 zynq 7030 on the same custom board.
Any updates on that topic?
The problem is still there (Address 0x0 returns: 0xdeaddead). I guess AXI doesn't work properly on that IP..?
Any help would be highly appreciated! Thank you
Hi,Can you extract all warnings regarding the axi_ad9122 from your log file and post a text file here?Andrei
Which log file do you mean? I do not use the tcl-script workflow for my custom project. Instead I have built up a block design in vivado.
If I search in vivado warnings, I have this warning:
[Synth 8-7023] instance 'axi_ad9122_0' of module 'system_axi_ad9122_0_0' has 39 connections declared, but only 33 given ["D:/hdl/projects/vbi-dab-us/vbi-dab-us/vbi-dab-us.srcs/sources_1/bd/system/synth/system.v":2275]
Also I only have problems on the ad9122 core (base addr 0x9c520000), the adc core and the axi_dmacs are working fine:
root@analog:~# devmem2 0x9c520000/dev/mem opened.Memory mapped at address 0xf7fa0000.Value at address 0x9C520000 (0xf7fa0000): 0xDEADDEADroot@analog:~# devmem2 0x99020000/dev/mem opened.Memory mapped at address 0xf785e000.Value at address 0x99020000 (0xf785e000): 0xA0162root@analog:~# devmem2 0x9c400000/dev/mem opened.Memory mapped at address 0xf7ba3000.Value at address 0x9C400000 (0xf7ba3000): 0x40262