HELLO ALL!
Kindly tell me about the trigger port on fmcjesdadc1 board. please elaborate its functionality, Can it be used to trigger all 4 channels at same time?In library folder there is an ip axi_adc_trigger, as shown in figure,
kindly tell me its integration in HDL referance design for 4 channel synchronized triggering.
Hi,I think you can use it. You need 2 axi_adc_trigger instances for all 4 channels.Connect the trigger_out_la of the first to the trigger_in of the second. This is the sync between the channels part.
The purpose of axi_adc_trigegr is to generate the sync signal(start capture) for the DMA signal.
You will also need the util_var_fifo and a BRM memory for history(samples before the trigger).We can only offer limited support regarding this since the core is design for M2k(adalm2000).Take a look at how it is integrated into the M2k. The easiest way is to build the project.
wiki.analog.com/.../axi_adc_triggerwiki.analog.com/.../util_var_fifowiki.analog.com/.../m2k
If you browse the wiki and github the m2k example is probably the answer for 90% of the questions regarding this.The axi_adc_trigger does not work on its own, you need software for it( wiki and github).
Andrei
Hello. i had modified the hdl-master-2018_r2 block diagram as
from adc_core_0 i take the data_a which is the data of channel A0, and split it into 2 16 bit chunks and give these two to adc_trigger_v1 and connect its triger pin with the G3 and G4 ports in constraint file. then i take the output of trigger core and concatinate them and insert it in adc_ad2950_cpack. After creating bit stream i make no-OS-master by providing its bit file and run the code. then i connect a trigger pulse with signal generator and provide a 1 Vpp and 500mVpp offset and 1kHz frequency. Ramp test runs successfully (without any inclution of trigger bit in data )and when i close test and just start adc then data is just noise in memory.
this is the data of ramp test in memory but when i omit test then
kindly guide the proper steps to deal with the setup.
Hi,Please use the hdl_2019_r1 release(Vivado 2018.3). The trigger bit is no longer present in the data. And the HDL is reflected in the latest axi_adc_trigger documentation.After the above can you share the tcl code (export from block design), much more details and easier to follow than a screenshot .Andrei