Hello,Beforehand I apologize for the possibly stupid questions. I am using Vivado 2017.2 and SDK and trying to create a project in which a PMod sensor connected to the one of the Zedboard's ports (iic for example) will send data via FMCOMMS2/3 to other zedboard which will recieve this data. So I started to modify the ad9361 reference design by adding one of the Pmod's block. I added PmodAQS block to the design, Run Connection Automation (in all fields i chose Auto) and make external pin "AQS_out". Should I chose another options (Master/slave clock source fields have same options like crossbar clock source)?
I added in the constrain file code, which works fine in standalone pmod example project (for jb which aren't in use in ad9361 reference design). After this manipulation Synthesis fails with this critical warnings:
I noticed that system.v upgraded after adding Pmod block in the design but system_top.v is not, there is no AQS or Pmod mentions in this file. For some reasons system_wrapper.v is upgraded only after manually replacing recreated hdl wrapper file. The project file hierarchy is as follows:
So, as i understand i need to modify this top file manually. The question is how to do this?
The top file of the manually created simply projects updating automatically, but they have another hierarchy of design sources: <design_wrapper>.v, <system>.bd, <design>.v instead this in ad9361 project - <top_file>.v, <design_wrapper>.v, <system>.bd, <design>.v.
I uploaded these .v files into google drive because i can't upload them here:https://drive.google.com/drive/folders/1F2DPSbcnaqSN88tTmZHeVewFdv_6428l?usp=sharing
Maybe i do all of this stuff initially incorrectly so maybe are there any other ways to do this project (add some pmods to reference design)?
I solve problem with system_top.v - now it generates bitstream, but with timing problem: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
What exactly are you referring to?
Crepe said: one of the Pmod's block
I apologize, maybe I expressed my thoughts incorrectly. I'm using Digilent Vivado Library (https://github.com/Digilent/vivado-library/releases) which contains all Vivado IP-blocks for Pmod sensors. In this project, I use exactly PmodAQS (from this library) as example to make sure that the main route of designing is correct and later i could same way add more ip-pmods to design.
Hi,I presume the timing issue is on the PMOD path, right?
There must be some example designs with the PMOD IP-blocks. Make sure you understand and apply the required constraints for the PMOD, used in those projects.Andrei