We're having a problem with the SOM/Carrier powering off when were trying to debug custom designs over JTAG. This could be trying to program the FPGA directly to assess interfaces with IBERT cores (ie: totally custom PL design) or through the SDK with a custom bare-metal PS design (FSBL + say an augmented HelloWorld program) and released ADI PL firmware. In all of these cases, everything starts off fine and operational and after what seems like a variable and random amount of time, the entire stack powers down.Is there a way to disable this auto-powerdown behavior in these cases? Maybe something we can add to the FSBL template design or otherwise?Thanks!
The black box of the ADM1266 can be read using the EVAL-ADP-I2C-USB adapter.
If the sequencer is powering off the board it will be logged in the black box.
Hi AndreiWe have a black-box on loan that we will try to debug with as well, but we're wondering if you've learned anything or made any headway since you replicated the issue.Thanks.
Please use ADI Power Studio to read the content of the black box and let us know which rail is causing the issues.
I am working this issue with Kevin and was able to read out the contents of the black box. The VDD1P3_DIG_A rail is reporting an OV Fault.
Please open the system rails tab, change the following values and program the device:
- OV Fault Level 1.450 Volts
- OV Glitch Filter 100uS
These settings should stop the board from rebooting until we find the right hardware fix (different values for the compensation network)