ADRV9009-ZU11EG + ADRV2CRR-FMC_RevB Auto Powerdown

We're having a problem with the SOM/Carrier powering off when were trying to debug custom designs over JTAG. This could be trying to program the FPGA directly to assess interfaces with IBERT cores (ie: totally custom PL design) or through the SDK with a custom bare-metal PS design (FSBL + say an augmented HelloWorld program) and released ADI PL firmware. In all of these cases, everything starts off fine and operational and after what seems like a variable and random amount of time, the entire stack powers down.

Is there a way to disable this auto-powerdown behavior in these cases? Maybe something we can add to the FSBL template design or otherwise?

Thanks!



Forgot to finish a sentence.
[edited by: HLKMay at 5:46 PM (GMT 0) on 9 Dec 2019]
Parents Reply
  • Mihai,

    We recently set up a second set of boards (SOM and Carrier) and programmed the ADM1266 with the updated configuration. These boards have been left powered-on and idle for the past two nights, and on both nights the ADM1266 recorded VDDA3P3_CLK under voltage faults and disabled the power supplies. Is this something that you have observed as well? Do you have any recommendations on how to proceed?

    Thanks,

    Mike

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