FPGA Reference Designs

Q&A ADRV9361-Z7035 minimum TX sampling rate

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ADRV9361-Z7035 minimum TX sampling rate

maitry.raval@azistaaerospace.com on Dec 4, 2019

Hello,

As Maximum sampling rate of TX in AD9361 is 61.44 MSPS , can you plesae provide the minimum TX sampling rate of AD9361?

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travisfcollins
Dec 6, 2019 in reply to maitry.raval@azistaaerospace.com +1 suggested
The AD9361 has a sigma-delta architecture and therefore utilizes decimation stages to provide the 12-bit resolution of the ADC. This requires running the ADC much faster than the actual output data rate…