Hello,
As Maximum sampling rate of TX in AD9361 is 61.44 MSPS , can you plesae provide the minimum TX sampling rate of AD9361?
The AD9361 has a sigma-delta architecture and therefore utilizes decimation stages to provide the 12-bit resolution of the ADC. This requires running the ADC much faster than the actual output data rate…
Actually,
Our datarate for TX side is 2 MBps , and in UG-570 manual, in table 10, it is written that for 2 MSPS sample rate required , set BBPLL frequency =1024 MHz , but I don't understand the calculation ?
PLease provide guidance.
The AD9361 has a sigma-delta architecture and therefore utilizes decimation stages to provide the 12-bit resolution of the ADC. This requires running the ADC much faster than the actual output data rate. To correctly set the clocks to for a specific data rate you can use this tool: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/filters
-Travis