Is it possible to phase align the data clock and feedback clock in a Zynq based system with an AD9361 (assuming perfectly matched trace length with appropriate IO Delays)? Looking at the RTL the feedback clock generator shown in Figure 78 is an MMCME2_ADV primitive. For an application I need to be able to guarantee this alignment relationship; is there additional work that would need to be done for dynamic adjustment of the MMCM or is there any guaranteed phase relationship between these lines? Thanks.
I don't think that we have an MMCM in the rx_clk to tx_clk loopback. As far as I know, we are receiving the clock with a BUFG and transmitting back to the device through an ODDR. As I see the problem, with this architecture you can not achieve the phase lock for these two clocks.
Can I ask what you are trying to achieve with this phase alignment?