Is it possible to phase align the data clock and feedback clock in a Zynq based system with an AD9361 (assuming perfectly matched trace length with appropriate IO Delays)? Looking at the RTL the feedback clock generator shown in Figure 78 is an MMCME2_ADV primitive. For an application I need to be able to guarantee this alignment relationship; is there additional work that would need to be done for dynamic adjustment of the MMCM or is there any guaranteed phase relationship between these lines? Thanks.
I don't think that we have an MMCM in the rx_clk to tx_clk loopback. As far as I know, we are receiving the clock with a BUFG and transmitting back to the device through an ODDR. As I see the problem…
I don't think that we have an MMCM in the rx_clk to tx_clk loopback. As far as I know, we are receiving the clock with a BUFG and transmitting back to the device through an ODDR. As I see the problem, with this architecture you can not achieve the phase lock for these two clocks.
Can I ask what you are trying to achieve with this phase alignment?
The goal is to generate a timing signal with a known phase relationship between what is received and transmitted. Even if they are not aligned the relationship must be known. With testing on the AD9361 on many cold starts it looks like the phase relationship is inconsistent at start up between the two sample clocks. With an MMCM I know you can align the phase of the input and output clocks and it looks like the necessary solution is to modify the ADI HDL to place an MMCM within the circuit to generate the feedback clock unless there is anything else you can think of to achieve this?
You could control the phase of the output clock through the DRP interface of the core, but I'm guessing you want an automatic phase adjustment. In that case yes, an MMCM would the best solution. Just switch the i_tx_clk instance to an MMCM and should work.