Phase Align Data Clock and Feedback Clock in AD9361/Zynq

Is it possible to phase align the data clock and feedback clock in a Zynq based system with an AD9361 (assuming perfectly matched trace length with appropriate IO Delays)? Looking at the RTL the feedback clock generator shown in Figure 78 is an MMCME2_ADV primitive. For an application I need to be able to guarantee this alignment relationship; is there additional work that would need to be done for dynamic adjustment of the MMCM or is there any guaranteed phase relationship between these lines? Thanks.