hi,i use the hdl project demo you provide.
i need to know the data order in the ip axi_adrv9009_core.
adc_os_data_i0[31:0]/adc_os_data_q0[31:0]/adc_os_data_i1[31:0]/adc_os_data_q1[31:0],when the sample rate is 491.52Msps,what is the data order????i want to get the right data from the 4x32bit data?how it comes?what should i do to get the right data??
Hi,
The data will be in order in memory as follow: i0_smp0, q0_smp0, i1_smp0, q1_smp0, i0_smp1, q0_smp1, ... Each sample consists of 2 bytes.
See the following wiki for more descriptive diagrams: https://wiki.analog.com/resources/fpga/docs/util_cpack
Thanks,
-Istvan
when i use the orx1(sample rate is 491.52),at one clk cycle,i get 128bit data ,the order is adc_os_data_i0[31:0]/adc_os_data_q0[31:0]/adc_os_data_i1[31:0]/adc_os_data_q1[31:0].what should i do to re-order.
At 491.52MHz, only one observation channel should be enabled. Please make sure your system is configured accordingly. In that case, you should have data only on ADC_OS_DATA_I0 and ADC_OS_DATA_Q0, and there should be two subsequent samples on each port.
i use the iio-scope to configure.you can see the picture.
i use bram to store data(adc_os_data_i0[31:0]/adc_os_data_q0[31:0]/adc_os_data_i1[31:0]/adc_os_data_q1[31:0]).
the data is like this.