hi,i use the hdl project demo you provide.
i need to know the data order in the ip axi_adrv9009_core.
adc_os_data_i0[31:0]/adc_os_data_q0[31:0]/adc_os_data_i1[31:0]/adc_os_data_q1[31:0],when the sample rate is 491.52Msps,what is the data order????i want to get the right data from the 4x32bit data?how it comes?what should i do to get the right data??
The data will be in order in memory as follow: i0_smp0, q0_smp0, i1_smp0, q1_smp0, i0_smp1, q0_smp1, ... Each sample consists of 2 bytes.
See the following wiki for more descriptive diagrams: https://wiki.analog.com/resources/fpga/docs/util_cpack
but the data is 32 bit ?what should i do