I am trying to modify the ADRV9009/ZCU102 reference design to loopback samples (Rx to Tx) within the fabric. I have connected the output of the util_adrv9009_rx_cpack module to the input of the axi_adrv9009_tx_dma via a custom module. This custom module receives 64-bit packed rx samples over a FIFO interface and outputs 128-bit packed tx samples over a AXI-streaming interface (tx_0 = rx_ch0i_0 rx_ch0q_0 rx_ch1i_0 rx_ch1q_0 rx_ch0i_1 rx_ch0q_1 rx_ch1i_1 rx_ ch1q_1). I changed the input interface of the axi_adrv9009_tx_dma module to axi-streaming.
It does not appear to be working, so I have a couple of questions:
I would be grateful for any advice.
Hi,You can do it much easier.https://github.com/analogdevicesinc/hdl/blob/master/library/axi_adrv9009/axi_adrv9009_tx_channel.v#L137
Write 0x08(loopback data) to the REG_CHAN_CNTRL_7 of each channel. See dac channel regmap.Andrei
The ultimate goal is to do some signal processing on the received signal within the fabric (filtering, for example), before sending the conditioned signal to the DACs for transmission. I think I require a more involved solution to do this?
You understand correctly - the DMAC is axi stream for src and dest. I went for this solution as I was trying to make minimal changes to the reference design, but happy to try your suggestion.
I will wire up my module to the input of the dac fifo using the dma_data, dma_ready, dma_xfer_last and dma_valid signals. I will remove the DMAC and its connections to the PS.
A couple of queries:
1) Can I leave the 'dma_xfer_req' of dac_fifo disconnected?
2) Should I tie 'bypass' of dac_fifo to a constant value to ensure that my samples are passed to the DAC?
2) When should I assert the last signal? At present I assert it every 1024 128-bit samples.
1. you can set dma_xfer_req to 1
2. tie 'bypass' to 1 if you want to stream contiguously from your module.
3. in bypass mode the 'last' is ignored.
Made these changes and behavior is the same - the ready signal does not go high. The confusing thing is that the ADI oscilloscope software starts at power up, and if I change the FPGA Settings -> Transmit/DDS -> Tx1 -> DDS Mode value to 'One CW Tone' I can see this tone on an analyzer. How is this possible if I have disconnected the transmit chain from the PS?
Correction. I changed the setting to DAC Buffer Output and seems to be working!
Last question on this topic, hopefully. When using iio.py to interface with the ADRV9009, what properties do I need to change to enable DMA transmit mode and enable all the DAC channels?
I am not familiar with iio.py, try getting info on that on the following forum: