We saw there already is AD9009 4T4R based on XiLinx, we're eager to know whether there's same 4T4R reference design for Altera FPGA. which is very importent for us.
Besides Notes: since ALTERA A10SOC DEMO BOARD has only single FMC Slot, which cann't support dual ADRV9009 to implement 4T4R. SInce you guys are FPGA experts, do you know whether there'is suitable ALTERA board which can be used to verify dual AD9009 4T4R capability ? Thanks in advance.
The Xilinx ADRV9009/4T4R is a custom board(https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg) we built, which takes into consideration the system clocking requirements for multichip synchonization. In the near future we don't plan to create a similar board with Intel FPGA. All the documentation for ADRV9009-ZU11EG-SOM will be public and can be used as a guideline on how to design a multi ADRV9009 system. Most of the software will work the same on an Intel FPGA and on a Xilinx FPGA so you should be able to use it in your system.
We're currently working on an FMCOMMS8 board, which is a dual ADRV9009 on an FMC form factor and it will work also with the A10SOC. We're in the process of validating the first prototypes and may take several months (hopefully weeks) until we have the project ported and working on A10SOC. I don't know the latest estimation dates when the board will be available for purchase.
Regarding putting two single ADRV9009 boards on a dual FMC carrier from Intel, I don't know a carrier which is definitely compatible with that format, as most of Intels boards have only one of the two FMC ports compatible with VITA FMC. We didn't look too much for one though.
Thanks AdrianC for the clarification.
1) Regarding of that "FMCOMMS8 board", do you have any detailed description links so I can take a look.
2) Another thing is : I was told ADI had released a new chipset named "ADRV9026", which is a 4 T/ 4 R transceiver, that's really great news. But it seems there's no HDL project in github till now, so we don't know how to start with it. Is there any schedule to provide similar "HDL / Linux OS/ so on" for customer integration from ADI perspective ?
Appreciate your kindly help as always.
1. https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms8-ebz this is the preliminary information about the board.
- the preliminary project for ZCU102: https://github.com/analogdevicesinc/hdl/tree/fmcomms8_zcu102
- the preliminary linux branch https://github.com/analogdevicesinc/linux/tree/fmcomms8_zcu102
The goal with this board is to connect it to ADRV9009-ZU11EG and have a 8T8R system. The block design for the final system can be seen at https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg/hardware
2. Our team doesn't have any drivers for ADRV9026 nor do we have a plan to support it in the near future.
Firstly of all, I'm really appreciated for your detailed explaination , It's very very useful. Hope your team can validate fmcomms8 quick as possible, so customers like us can take as reference for A10 design as well.
Regarding of Dual AD9009 , you mentioned that " must takes into consideration the system clocking requirements for multichip synchonization ". To be honest, I don't understand what's the major difference of system clocking requirements between single AD9009 design, and dual AD9009 design . Can you explain a bit more .
What's clocking requirements should pay attentions to when we do our own customer design (dual AD9009 board)? Is there any doc to describe this detaiil.
Thanks & Best Regards
It's the basic JESD204B requirements:
- all the clocks in the system to be generated from a single crystal
- device clock and SYSREF to meet setup and hold requirements for the ADRV9009
- device clock and SYSREF sent to the FPGA to be source synchronous
For the multichip synchronization procedure of ADRV9009 you need to be able to stop SYSREF. We encountered a problem with the first approach of using HMC7044 and you can see in Rev B of the ADRV9009-ZU11EG schematic the changes we did to be able to successfully stop SYSREF.
If the ADRV9009 have independent links and don't need to be synchronized, then clocking can be a bit relaxed, but still will need to meet JESD204B requirements for each ADRV9009 and FPGA independently.