I already asked a question about dma modes as the below link.
I got some help (thanks to travisfcollins) but still I cannot figure out some basic structure I should use.
I explain the jobs I have done until now again here. I set a timer in the Xilinx SDK and once the timer triggers the interrupt, Rx and Tx along with their dmas are enabled to send and receive data (just one time) and then I will disable all of them until the next interrupt. Rx and TX are connected by a RF cable on the board. Tx source dma is configured as stream and its destination as MM (Memory Mapped). Rx source dma is MM and its destination is stream. Now, I want to remove the timer and do the same thing. It means I need the dma not to interrupt CPU (to avoid any missing data) and I was thinking this means send/receive data in a cyclic scheme with 2D transfer enabled.
Since our group did some designs either in Vivado or Xilinx SDK I cannot switch to iio (as mentioned in my previous posted question) at this stage. I will explain the problem I have below and I do appreciate it if anybody could help me to find out the solution.
I am a beginner in this area and I plan to stream data from Rx to FPGA and then by using Ethernet send them to PC continuously with the highest possible speed. I am thinking, for Rx I should use the AXI stream mode as source and AXI MM as destination. However, data should be written into the memory one after another to make sure no data will be missed and this means utilizing a 2D transfer is a must. My first question is that whether AXI Stream as source and 2D transfer are the right choices? I read from (https://wiki.analog.com/resources/fpga/docs/axi_dmac#cyclic_transfers) that AXI Stream dose not care about 2D transfer if my understanding is right. I tried this but I did not get any data in 2D form. So, Do I need to use MM as source dma to be able to use 2D transfer? Also, I need to do the same process over and over as mentioned above, so I could use the cyclic mode because it is repeating automatically. But actually I am not sure if these all modes are working together at the same time. I could not find enough information in web, please let me know if anyone can introduce some online docs.
Would you please help me to find the dma modes and give me some hits to find the right direction?
For Rx you can have a 2D transfer and stream as a source. The destination (MM) will be organized in a 2D way. Make sure you set correctly the DEST_STRIDE and Y_LENGTH registers. Eventually share a register dump so we can have a look.
I do not recommend cyclic for Rx since the DMAC does not give any interrupts or feedback in this mode to show the transfer progress. It will overwrite the same memory area over and over again.
Thanks a lot for your help. I will try that and let you know the result.
Another question I have. If cyclic mode is not a good choice, I should wait for a transfer to be done and then start the next one. Suppose data is coming continuously, will Rx miss any data during dma reconfiguration or the existing buffer within dma can handle it automatically?
mamad said:while dma is filling up the memory, there is enough time to read the data and send them out.
on the application side which suppose to forward the data to ethernet how do you know how much data did the DMA captured in your memory buffer? As I said in cyclic mode the DMAC does not give you any interrupt or feedback.
If 16MB limit is a problem you can increase that by adjusting the DMA_LENGTH_WIDTH parameter of the core.
Instead of cyclic you could use a double/three buffer system, first fill with the dma a buffer. while dma is writing the second buffer you send out the first one and so on, keep one buffer difference between the reader and writer.
Yes, you are right, there is no way to get feedback in cyclic mode and that would be a problem. Thanks for your help.If my understanding is right, the only problem would be the time that dma switch between two buffers. In the above figure of received Rx sine wave, I firstly configure dma to write into one memory address while I am recording data from the secondary address and then reconfigure dma to switch its memory destination like what you suggested. However, the time dma is switching between these two memories some data are missing (as shown in the figure). Please let me know if I did the same scenario you mentioned?
You can queue up a transfer to the DMAC in advance so it will switch smoothly when it finished the first transfer.
Suppose you have two buffers A and B,
First you commit the A that will start immediately and commit B (this will be queued)
in the transfer end interrupt you will commit the next descriptor (A or B whatever is the next one) then process (send to Ethernet or else) the data from the currently finished buffer.
Thank you very much for your help. I will try that and let you know the results.
I tried the queue method you mentioned above and it works perfectly. I really appreciate your help.