I already asked a question about dma modes as the below link.
I got some help (thanks to travisfcollins) but still I cannot figure out some basic structure I should use.
I explain the jobs I have done until now again here. I set a timer in the Xilinx SDK and once the timer triggers the interrupt, Rx and Tx along with their dmas are enabled to send and receive data (just one time) and then I will disable all of them until the next interrupt. Rx and TX are connected by a RF cable on the board. Tx source dma is configured as stream and its destination as MM (Memory Mapped). Rx source dma is MM and its destination is stream. Now, I want to remove the timer and do the same thing. It means I need the dma not to interrupt CPU (to avoid any missing data) and I was thinking this means send/receive data in a cyclic scheme with 2D transfer enabled.
Since our group did some designs either in Vivado or Xilinx SDK I cannot switch to iio (as mentioned in my previous posted question) at this stage. I will explain the problem I have below and I do appreciate it if anybody could help me to find out the solution.
I am a beginner in this area and I plan to stream data from Rx to FPGA and then by using Ethernet send them to PC continuously with the highest possible speed. I am thinking, for Rx I should use the AXI stream mode as source and AXI MM as destination. However, data should be written into the memory one after another to make sure no data will be missed and this means utilizing a 2D transfer is a must. My first question is that whether AXI Stream as source and 2D transfer are the right choices? I read from (https://wiki.analog.com/resources/fpga/docs/axi_dmac#cyclic_transfers) that AXI Stream dose not care about 2D transfer if my understanding is right. I tried this but I did not get any data in 2D form. So, Do I need to use MM as source dma to be able to use 2D transfer? Also, I need to do the same process over and over as mentioned above, so I could use the cyclic mode because it is repeating automatically. But actually I am not sure if these all modes are working together at the same time. I could not find enough information in web, please let me know if anyone can introduce some online docs.
Would you please help me to find the dma modes and give me some hits to find the right direction?
You can queue up a transfer to the DMAC in advance so it will switch smoothly when it finished the first transfer.
Suppose you have two buffers A and B,
First you commit the A that will start immediately…
For Rx you can have a 2D transfer and stream as a source. The destination (MM) will be organized in a 2D way. Make sure you set correctly the DEST_STRIDE and Y_LENGTH registers. Eventually share a register dump so we can have a look.
I do not recommend cyclic for Rx since the DMAC does not give any interrupts or feedback in this mode to show the transfer progress. It will overwrite the same memory area over and over again.
Thanks a lot for your help. I will try that and let you know the result.
Another question I have. If cyclic mode is not a good choice, I should wait for a transfer to be done and then start the next one. Suppose data is coming continuously, will Rx miss any data during dma reconfiguration or the existing buffer within dma can handle it automatically?
I tried 2D transfer for Rx (that is set in stream mode no-cyclic) with X_LENGTH = 8192 and Y_LENGTH = 1 and different values of DEST_STRIDE ((such as 8192, 8192*2). The first row of data is received well but there is no valid data in the second row. It means 2D transfer is not working. Please let me know if you have any idea about 2D transfer problem.
Also, I tried with 1D Rx transfer in stream mode (no-cyclic). When dma finished (and its interrupt is triggered), the next transfer will be started. It means I should receive data continuously and for a sine wave there would be a complete sine wave in Rx output. However, there are some missing data between finishing the previous data and starting the new one. I think there should be the same problem for 2D transfer and still I think cyclic mode (or FIFO) is the solution for this issue. I got a screen shot below to show the problem.
Please let me know if other Rx modes is the solution for this issue.
keep in mind that X_LENGTH and Y_LENGTH must be set with -1 value.
Sorry, I do not understand why X_LENGTH and Y_LENGTH should be set to -1. Would you please let me know for which mode (or condition) they must be -1?
This is how the hdl code is built. If you want to transfer 2 "lines" of 128 bytes each you need to write 127 to the X_LENGTH and Y_LENGTH must be set to 1.
However the DEST_STRIDE must be set with full length, 128.