I am trying to implement the Xilinx iBERT IP to accept PRBS data from the Talise (ADVR9008) chip and enable me to look at the eye diagram.
Initially I tried taking the ZCU102 reference design and deleting the talise_tmc block and all associated IP; replacing it with the Xilinx JESD_PHY and iBERT IP. The idea was, with a bit of editing of the device tree in peta-linux environment, I would be able to remove keep just the SPI driver to set-up the Talise chip and I could use iio to set the BIST PRBS mode or the framer. Unfortunately I encountered the knock on effect of losing comms with the device over SPI and not having the iio commands available.
My next thought was to go back to the original reference design and see if I could just instantiate the iBERT IP and plumb it into the existing ADI IP. It looks like most of the ports required come up to the top of the util_adxcvr block as the "up_*" signals, then go off to the axi_adxcvr IP block. I am reluctant to blindly try reconnecting and editing this design as I suspect it will all stop working again!
Any suggestions on the best way for me to proceed to try and get the eye diagram working to test the link from the Talise to the FPGA transceiver (uni-directional no loopback)?