I have an old project where an AD9265 interfaces a spartan6 FPGA (no optión to change the hw) in LVDS mode
Recently we are experiencing problems with the interface under some temperature conditions. To be honest we have never understood correctly the datasheet specs so probably the constraints are not correctly set, but the interface worked.
In one hand I need help to understand de Tskew (DCO to dat skew) value in the datasheet, which I understand is the most critical to make the interface work.
It says min->-0.3/max->1.2. Which those values I understand that the data is stable 1.2ns after the DCO edge and remain stable till 0.3 before the next edge (positive to negative??). Is this assumption correct or does it mean that the data is stable 0.3 ns before the clock edge and remains stable till 1.2 after it?
Anyway, we are using the DCO to store the values from the ADC in a memory (after a IDDR2 that also uses DCO and not(DCO) in C0 and C1 inputs). what should be the correct OFFSET = IN xx VALID yy ns BEFORE for this device?
I hope someone can help us with this problem.
Did you try to tune your interface using the registers 0x16 and 0x17? Having a source synchronous interface, you need to make sure that your setup respects the setup and hold requirements of the receive buffer (IDDR2 in your case).
Initially, I would switch the DCO polarity (register 0x16), and if that does not help, you can try to apply an offset to the DCO and see how the interface's state changes. The best method is to set up a test output for the device (one of the supported PN sequence) and implement a PN monitor inside the FPGA, then test the interface with all the DCO offset and see where the monitor locks.
In my understanding, the DCO to data skew just defines a variable time difference (uncertainty) between a DCO and data edges.
Our axi_ad9265 HDL IP has an integrated PN monitor for tunning purposes. You can try to use it if you're not using already,