I am the beginner user of adrv9371 on Xilinx Zc706. I got enough information about adrv9371 and able to send and receive data when Rx and Tx channel are connected together.
I plan to configure adrv9371 to be able to receive all data coming from Rx and send it to PC.
From the provided code (dac_core.c), it seems that there are several modes for sending/receiving data such as DMA_STREAM, DMA_CYCLIC and DMA_PLDDR_FIFO. Is there other documentations available that provide more information about such streaming modes? What is fastest mode I can use to stream all data from Rx and how can I configure the adrv9371 to use such mode?
Thanks for your help
Moving to FPGA subspace.
If you just want to stream data back to a PC, utilize the IIO drivers which are integrated into the standard SD card.
AD9371 IIO driver: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9371
The easiest way to interface with the driver is either with:
These are all based on the libIIO interface: https://wiki.analog.com/resources/tools-software/linux-software/libiio
Streaming data back will be limited based on the networking interface of the ZC706. However, you can do large burst captures which can be several million samples at the full rate of the transceiver.
Cyclic modes of TX and RX are all controlled from software. I would recommend ignoring the HDL and No-OS components until you are modifying HDL and moving towards a fully embedded design.
The API to control the cyclic nature of the buffers will be specific to the software you use (MATLAB/Python/C...) but they are all just creating cyclic buffers with the libIIO API under the hood:https://analogdevicesinc.github.io/libiio/group__Buffer.html
Doc on python buffer management: https://analogdevicesinc.github.io/pyadi-iio/buffers/index.html
Thanks for your help. For my curiosity I checked "Cyclic Transfer Support" in the Rx DMA adrv9371 within Vivado design and then I could not pass "Generate output products" step in the design flow with several errors such the one below:
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_ad9371_rx_dma'. Failed to generate 'Synthesis' outputs:
It means more HDL work needed to enable cyclic DMA among the block design.
Would you please let me know other than the software/platform you mentioned (libIIO API), is it possible to use Xilinx SDK to do such a cyclic transferring?
Why do you want to do cyclic transfers on RX? It would simply repeat the same data over and over, only repeating the first buffer received from the transceiver.
It seems my understanding from cyclic mode is not right then. Let me explain more details.
I want to send and receive data continuously. At the moment I have a timer and once timer trigger the interrupt, I will enable Rx and Tx along with DMA to send and receive data and then I will disable them all until the next interrupt. Rx and TX are connected by a RF cable on the board. Now, I want to remove the timer and do the same thing. It means I need DMA not to interrupt CPU (to avoid any missing data) and I was thinking this means send/receive data in a cyclic scheme.
Please let me know if I need to describe more details and if you have any idea how to make this work.
Cyclic mode means that the DMA simply repeats the same data, so this really only makes sense on TX if you constantly want to send the DAC the same data.
How the DMA+Software interface works is the following:
- When a buffer is created on the RX side (https://github.com/analogdevicesinc/libiio/blob/master/examples/ad9371-iiostream.c#L249) it will start to capture data into DDR, which will actually collect several buffers inside DDR in a circular buffer queue.
- Then when you do a refill (https://github.com/analogdevicesinc/libiio/blob/master/examples/ad9371-iiostream.c#L272) it will pull a single buffer from this circular queue and allow room for more data. As long as you can keep up by pulling buffers fast enough you will not drop data.
Generally people create a cyclic buffer on the TX side first, then start pulling buffers from RX.
Thanks for your help. We also did the same cyclic buffer in Xilinx SDK for the interrupt based project I explain above. I will read the materials you suggested and if I have a question I will let you know.