I'm doing initial analysis and planning for designing a custom RF board with two AD9361 chips to interface with my FPGA board. The FPGA board that I want to use is the MYIR Z-turn board. The board uses Zynq-7020 SoC as a core device and has two pin header connectors on the bottom side that I want to use for interfacing.
I'm currently doing pin mapping/planning and quickly found out that I do not have enough I/Os for both of the AD9631 chips. More specifically, I do not have enough CMOS I/Os to interface the 8 control outputs signals (16 in total from both of the chips) to the Zynq device. All other pins fit nicely and I have no problem with mapping them and interafcing to my FPGA.
So, I wanted to ask what are possible options here?
I know that control outputs are not required to operate the AD9631 chips as all of that data can be read via SPI from registers, so I ould just leave them floating (unused). However I think that they can be valuable, especially when developing or debugging, so I would prefer to use those.
The other thing that I thought of was to use parallel-to-serial ICs (like two Nexperias 74LV165A chips) which would reduce the required pin count from 16 down to 4. However, I'm worried if this solution would work as intended and if there won't be any stability problems because of asynchronus inputs to PISO converters.
Are there maybe any other options that I have not though of?
From a FPGA stand point using parallel-to-serial ICs should work unless you need the pins responding in real time. If the delays become a problem the pins would need to be connected directly to the FPGA. Another thing you can use are I2C GPIO controllers, but these would have the same problem with the delays.
You might get a more in depth answer on this Design Support Forum.
Also the Wiki contains example boards that might provide good insight on this as they are completely open source.