ADV7511 ZC706 HDL Design Error

Hello, I am using a Zynq ZC706 FPGA board trying to get a Linux HDMI project running. I have used 2 different methods to try to build the project from hdl-master, 1 in Windows and 1 in Linux. I have run the make file contained in ../projects/adv7511/zc706 in Linux and used source ../scripts/adi_make.tcl in Windows. They both return the following error:

### ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell axi_hp0_interconnect
ERROR: [BD 5-7] Error: running create_bd_cell.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}"
(procedure "ad_ip_instance" line 3)
invoked from within
"ad_ip_instance smartconnect axi_hp0_interconnect"
invoked from within
"if {$sys_hp0_interconnect_index < 0} {
set p_name_int sys_ps7/S_AXI_HP0
set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
..."
invoked from within
"if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
if {$sys_hp0_interconnect_index < 0} {
set p_name_int sys_ps7/S_AXI_HP0
set_property CONF..."
(procedure "ad_mem_hpx_interconnect" line 24)
invoked from within
"ad_mem_hpx_interconnect "HP0" $p_clk $p_name"
invoked from within
"if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}"
(procedure "ad_mem_hp0_interconnect" line 7)
invoked from within
"ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0"
(file "C:/Vivado_Projects_-_IDB/Zynq_Tests/hdl-master/projects/common/zc706/zc706_system_bd.tcl" line 231)

while executing
"source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl"
(file "system_bd.tcl" line 2)

while executing
"source system_bd.tcl"
(procedure "adi_project" line 127)
invoked from within
"adi_project adv7511_zc706"
(file "system_project.tcl" line 6)

How can I get past this and generate the Vivado Block Design?

Thank you.