Ad 9371 No OS ADC Data All Noise?

Hi,

We are trying to use the Xilinx evaluation board ZCU 106 and the RadioVerse AD 9371 RF card. We followed the steps in

https://wiki.analog.com/resources/eval/user-guides/mykonos/no-os-setup

1. Feed 30.72MHz reference clock to J401

2. Build HDL with Vivado 2018.3 from https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9371x/zc706 (master branch)

3. Use the C source files from https://github.com/analogdevicesinc/no-OS/tree/2018_R2/ad9371 (2018_R2 branch)

4. Build xsdk project etc.

Initially, the settings in MyK.c didn't work and the main function in headless.c just froze. We downloaded the RadioVerse Transceiver Evulations Software, generated a new MyK.c, that didn't work either. However, after comparing the difference MyK.c versions, by trial and error, we identified the key difference under rxFramer

static mykonosJesd204bFramerConfig_t rxFramer =
{
    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
    4,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
    0x03,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
    0x10,           /* serializerLaneCrossbar*/
    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
};

Now, the headless.c runs as follows:

Please wait...
vcxo_Frequency_Hz 122880000 refA_Frequency_Hz 30720000 outFrequency_Hz 122880000
RX_XCVR (GTX2) initialization OK
TX_XCVR (GTX2) initialization OK
RX_OS_XCVR (GTX2) initialization OK
MCS successful
CLKPLL locked
AD9371 ARM version 5.1.1
PLLs locked
Calibrations completed successfully
DeframerStatus = 0x21
dac_setup dac core initialized (122 MHz).
adc_setup adc core initialized (123 MHz).

However, the signal captured by adc_capture looks like all noise. We use xsdk debugger and dump the memory to study. Pretty much all the I/Q samples are just small value random numbers. We injected a pure tone to both RX1 J200 and RX2 J201 and the I/Q samples never made any sense.

Please identify where the problem may lie.

Thanks.

  • 0
    •  Analog Employees 
    on Oct 17, 2019 8:42 PM over 1 year ago

    Hi,

    Have a look here: https://github.com/analogdevicesinc/no-OS/tree/master/projects/ad9371/src - all the project's necessary files (including API and an example profile) can be found here.

    Thanks,
    Dragos

  • Your Jesd path for TX is failing.

    /**
     * \brief Reads the transceiver's deframer status
     *
     * <B>Dependencies</B>
     * - device->spiSettings
     *
     *   deframerStatus  |  Bit Name                |  Description
     *   ----------------|--------------------------|---------------------------------------------
     *              [7]  | Unused                   | Unused
     *              [6]  | Deframer IRQ             | This bit indicates that the IRQ interrupt was asserted.
     *              [5]  | Deframer SYSREF Received | When this bit is set, it indicates that the SYSREF pulse was received by the deframer IP
     *              [4]  | Deframer Receiver Error  | This bit is set when PRBS has received an error.
     *              [3]  | Valid Checksum           | This bit is set when the received ILAS checksum is valid.
     *              [2]  | EOF Event                | This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS
     *              [1]  | EOMF Event               | This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS
     *              [0]  | FS Lost                  | This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters)
     *
     *
     * \param device is a pointer to the device settings structure
     * \param deframerStatus is the deframer status byte read
     *
     * \retval MYKONOS_ERR_OK Function completed successfully
     * \retval MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM Function parameter deframerStatus has NULL pointer

    Most probably you are failing at ILAS state. You can follow the description above to track the error. Deframer status should not be 0x21.

  • Thanks but as I stated, I was only interested in getting the ADCs working. Regardless of the DAC status, I don't think ILAS states are related between TX and RX paths?

  • Hi,

    I created a new XSDK project using the new GIT repository. However, the same problem persists. The ADC data captured in headless.c

    axi_dmac_transfer(rx_dmac, DDR_MEM_BASEADDR + 0x800000, 16384 * 8);

    do not make any sense. I injected a pure tone 2.525GHz with around -10dBm to either RX1 J200 or RX2 J201. I did not touch myk.c and the RX LO is at default 2.5GHz. The memory dump of address 0x800000 (DDR_MEM_BASEADDR is 0x0) showed basically very small values (less than 100 so basically 6 or 7 bits at most). I tried decreasing the pure tone power and I did see the small values decrease to around 50. However, it was impossible to make out the waveform and it looked like just noise.

    Just to be sure, the memory dump should be int16 I/Q interleaved correct?

  • Here is the print out of the new headless.c

    Please wait...
    rx_clkgen: MMCM-PLL locked (122880000 Hz)
    tx_clkgen: MMCM-PLL locked (122880000 Hz)
    rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Calibrations completed successfully
    tx_adxcvr: OK (4915200 kHz)
    rx_adxcvr: OK (4915200 kHz)
    rx_os_adxcvr: OK (4915200 kHz)
    rx_jesd status:
            Link is enabled
            Measured Link Clock: 122.882 MHz
            Reported Link Clock: 122.880 MHz
            Lane rate: 4915.200 MHz
            Lane rate / 40: 122.880 MHz
            Link status: DATA
            SYSREF captured: Yes
            SYSREF alignment error: No
    rx_jesd lane 0 status:
            CGS state: DATA
            Initial Frame Synchronization: Yes
            Lane Latency: 1 Multi-frames and 75 Octets
            Initial Lane Alignment Sequence: Yes
            DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
            K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
            FCHK: 0x47, CF: 0
            ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
            FC: 4915200 kHz
    rx_jesd lane 1 status:
            CGS state: DATA
            Initial Frame Synchronization: Yes
            Lane Latency: 1 Multi-frames and 76 Octets
            Initial Lane Alignment Sequence: Yes
            DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
            K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
            FCHK: 0x48, CF: 0
            ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
            FC: 4915200 kHz
    tx_jesd status:
            Link is enabled
            Measured Link Clock: 122.882 MHz
            Reported Link Clock: 122.880 MHz
            Lane rate: 4915.200 MHz
            Lane rate / 40: 122.880 MHz
            SYNC~: deasserted
            Link status: DATA
            SYSREF captured: Yes
            SYSREF alignment error: No
    rx_os_jesd status:
            Link is enabled
            Measured Link Clock: 122.882 MHz
            Reported Link Clock: 122.880 MHz
            Lane rate: 4915.200 MHz
            Lane rate / 40: 122.880 MHz
            Link status: DATA
            SYSREF captured: Yes
            SYSREF alignment error: No
    rx_os_jesd lane 0 status:
            CGS state: DATA
            Initial Frame Synchronization: Yes
            Lane Latency: 2 Multi-frames and 10 Octets
            Initial Lane Alignment Sequence: Yes
            DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
            K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
            FCHK: 0x43, CF: 0
            ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
            FC: 4915200 kHz
    rx_os_jesd lane 1 status:
            CGS state: DATA
            Initial Frame Synchronization: Yes
            Lane Latency: 2 Multi-frames and 8 Octets
            Initial Lane Alignment Sequence: Yes
            DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
            K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
            FCHK: 0x44, CF: 0
            ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
            FC: 4915200 kHz
    tx_dac: Successfully initialized (245764160 Hz)
    rx_adc: Successfully initialized (122882080 Hz)
    Done

    In addition, I used the memory dump command

    mrd -bin -file dump.bin 0x800000 131072