Ad 9371 No OS ADC Data All Noise?


We are trying to use the Xilinx evaluation board ZCU 106 and the RadioVerse AD 9371 RF card. We followed the steps in

1. Feed 30.72MHz reference clock to J401

2. Build HDL with Vivado 2018.3 from (master branch)

3. Use the C source files from (2018_R2 branch)

4. Build xsdk project etc.

Initially, the settings in MyK.c didn't work and the main function in headless.c just froze. We downloaded the RadioVerse Transceiver Evulations Software, generated a new MyK.c, that didn't work either. However, after comparing the difference MyK.c versions, by trial and error, we identified the key difference under rxFramer

static mykonosJesd204bFramerConfig_t rxFramer =
    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
    4,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
    0x03,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
    0x10,           /* serializerLaneCrossbar*/
    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/

Now, the headless.c runs as follows:

Please wait...
vcxo_Frequency_Hz 122880000 refA_Frequency_Hz 30720000 outFrequency_Hz 122880000
RX_XCVR (GTX2) initialization OK
TX_XCVR (GTX2) initialization OK
RX_OS_XCVR (GTX2) initialization OK
MCS successful
CLKPLL locked
AD9371 ARM version 5.1.1
PLLs locked
Calibrations completed successfully
DeframerStatus = 0x21
dac_setup dac core initialized (122 MHz).
adc_setup adc core initialized (123 MHz).

However, the signal captured by adc_capture looks like all noise. We use xsdk debugger and dump the memory to study. Pretty much all the I/Q samples are just small value random numbers. We injected a pure tone to both RX1 J200 and RX2 J201 and the I/Q samples never made any sense.

Please identify where the problem may lie.