AD9361 TXFIR int 0 RXFIR dec 0 mode Highest OSR

Hi,

These are the inputs given by us for configuring AD9361.

{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies 

{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

AD9361_TXFIRConfig tx_fir_config = {    // BPF PASSBAND 3/20 fs to 1/4 fs
    1, // tx
    -6,  tx_gain
    2 ,//tx_int
{1,-6,-28,-62,-80,-56,11,68,54,-29,-98,-61,64,142,59,-122,-195,-35,210,246,-26,-329,-280,141,476,273,-326,-636,-193,595,786,3,-957,-889,351,1424,890,-953,-2027,-696,1997,2886,76,-4178,-4612,2199,13771,22755,22755,13771,2199,-4612,-4178,76,2886,1997,-696,-2027,-953,890,1424,351,-889,-957,3,786,595,-193,-636,-326,273,476,141,-280,-329,-26,246,210,-35,-195,-122,59,142,64,-61,-98,-29,54,68,11,-56,-80,-62,-28,-6,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    128, // tx_coef_size
    {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000}, //{0, 0, 0, 0, 0, 0}, // tx_path_clks[6]
     1330000 // tx_bandwidth
};

but we are getting error ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSR
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit".

please give the feedback how to solve thiis error.

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