Hi,
These are the inputs given by us for configuring AD9361.
{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 1, // tx -6, tx_gain 2 ,//tx_int{1,-6,-28,-62,-80,-56,11,68,54,-29,-98,-61,64,142,59,-122,-195,-35,210,246,-26,-329,-280,141,476,273,-326,-636,-193,595,786,3,-957,-889,351,1424,890,-953,-2027,-696,1997,2886,76,-4178,-4612,2199,13771,22755,22755,13771,2199,-4612,-4178,76,2886,1997,-696,-2027,-953,890,1424,351,-889,-957,3,786,595,-193,-636,-326,273,476,141,-280,-329,-26,246,210,-35,-195,-122,59,142,64,-61,-98,-29,54,68,11,-56,-80,-62,-28,-6,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 128, // tx_coef_size {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000}, //{0, 0, 0, 0, 0, 0}, // tx_path_clks[6] 1330000 // tx_bandwidth};
but we are getting error ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSRad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit".
please give the feedback how to solve thiis error.
Moving to FPGA subspace. Someone here will be able to verify the changes done.
Please use the filter wizard tool to create a custom profile.
Please refer to bellow posts,
https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88114/ad9361_dig_tune-tuning-failed-when-using-no-os-drivers
https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88110/fir-structure-parameter-initialization-error
we used this function in main.c ad9361_trx_load_enable_fir(ad9361_phy, rx_fir_config, tx_fir_config)" ,and still we got same error "ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit.
I'm attaching main.c file from SDK.
We changed the rx_path_clock_frequencies[6],tx_path_clock_frequencies[6],rf_rx_bandwidth_hz,rf_tx_bandwidth_hz are made to zero in default_init_param in SDK. Desired values are given in tx_fir_config,rx_fir_config structure.
/***************************************************************************//** * @file main.c * @brief Implementation of Main Function. * @author DBogdan (dragos.bogdan@analog.com) ******************************************************************************** * Copyright 2013(c) Analog Devices, Inc. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of Analog Devices, Inc. nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * - The use of this software may or may not infringe the patent rights * of one or more patent holders. This license does not release you * from the requirement that you obtain separate licenses from these * patent holders to use this software. * - Use of the software either in source or binary form, must be run * on or directly connected to an Analog Devices Inc. component. * * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ /******************************************************************************/ /***************************** Include Files **********************************/ /******************************************************************************/ #include "config.h" #include "ad9361_api.h" #include "parameters.h" #include "platform.h" #ifdef CONSOLE_COMMANDS #include "command.h" #include "console.h" #endif #ifdef XILINX_PLATFORM #include <xil_cache.h> #endif #if defined XILINX_PLATFORM || defined LINUX_PLATFORM || defined ALTERA_PLATFORM #include "adc_core.h" #include "dac_core.h" #endif /******************************************************************************/ /************************ Variables Definitions *******************************/ /******************************************************************************/ #ifdef CONSOLE_COMMANDS extern command cmd_list[]; extern char cmd_no; extern cmd_function cmd_functions[11]; unsigned char cmd = 0; double param[5] = {0, 0, 0, 0, 0}; char param_no = 0; int cmd_type = -1; char invalid_cmd = 0; char received_cmd[30] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; #endif /////////////////////////////////////////////////////////// //Added by Mable for Debug uint32_t fn1,fn2,fn3; uint8_t tx_ch=0; uint8_t en_dis_fir; ///////////////////////////////////////////////////////////////////////////////////////// AD9361_InitParam default_init_param = { /* Device selection */ ID_AD9361, // dev_sel /* Identification number */ 0, //id_no /* Reference Clock */ 40000000UL, //reference_clk_rate /* Base Configuration */ 0,//1, //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable 0,//1, //one_rx_one_tx_mode_use_rx_num *** adi,1rx-1tx-mode-use-rx-num 0,//1, //one_rx_one_tx_mode_use_tx_num *** adi,1rx-1tx-mode-use-tx-num 1, //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable 0, //frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable 0, //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable 0, //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable 0, //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns 0, //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns 0, //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable 0, //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable 0, //external_rx_lo_enable *** adi,external-rx-lo-enable 0, //external_tx_lo_enable *** adi,external-tx-lo-enable 5, //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask 6, //dc_offset_attenuation_high_range *** adi,dc-offset-attenuation-high-range 5, //dc_offset_attenuation_low_range *** adi,dc-offset-attenuation-low-range 0x28, //dc_offset_count_high_range *** adi,dc-offset-count-high-range 0x32, //dc_offset_count_low_range *** adi,dc-offset-count-low-range 0, //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable MAX_SYNTH_FREF, //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz 0, // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable /* ENSM Control */ 0, //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable 0, //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable /* LO Control */ 1450000000UL,//, //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz 1450000000UL,//1450000000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz 1, //tx_lo_powerdown_managed_enable *** adi,tx-lo-powerdown-managed-enable /* Rate & BW Control */ {0, 0, 0, 0, 0, 0},//{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies {0, 0, 0, 0, 0, 0},//{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies 0,//3362055,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz 0,//3362055,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz /* RF Port Control */ 0, //rx_rf_port_input_select *** adi,rx-rf-port-input-select 0, //tx_rf_port_input_select *** adi,tx-rf-port-input-select /* TX Attenuation Control */ 7500,//7500,//10000,//1000, //tx_attenuation_mdB *** adi,tx-attenuation-mdB 0, //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable /* Reference Clock Control */ 0, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable {7,5900},//{8, 5920}, //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune CLKOUT_DISABLE, //clk_output_mode_select *** adi,clk-output-mode-select /* Gain Control */ 2, //gc_rx1_mode *** adi,gc-rx1-mode 2, //gc_rx2_mode *** adi,gc-rx2-mode 58, //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh 4, //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size 47, //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh 8192, //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration 0, //gc_dig_gain_enable *** adi,gc-dig-gain-enable 800, //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh 704, //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh 24, //gc_low_power_thresh *** adi,gc-low-power-thresh 15, //gc_max_dig_gain *** adi,gc-max-dig-gain /* Gain MGC Control */ 2, //mgc_dec_gain_step *** adi,mgc-dec-gain-step 2, //mgc_inc_gain_step *** adi,mgc-inc-gain-step 0, //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable 0, //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable 0, //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode /* Gain AGC Control */ 10, //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter 2, //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps 0, //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable 10, //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter 4, //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size 3, //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter 1000, // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us 0, //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable 0, //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable 10, //agc_inner_thresh_high *** adi,agc-inner-thresh-high 1, //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps 12, //agc_inner_thresh_low *** adi,agc-inner-thresh-low 1, //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps 10, //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter 2, //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps 10, //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter 5, //agc_outer_thresh_high *** adi,agc-outer-thresh-high 2, //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps 18, //agc_outer_thresh_low *** adi,agc-outer-thresh-low 2, //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps 1, //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us 0, //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable /* Fast AGC */ 64, //fagc_dec_pow_measuremnt_duration *** adi,fagc-dec-pow-measurement-duration 260, //fagc_state_wait_time_ns *** adi,fagc-state-wait-time-ns /* Fast AGC - Low Power */ 0, //fagc_allow_agc_gain_increase *** adi,fagc-allow-agc-gain-increase-enable 5, //fagc_lp_thresh_increment_time *** adi,fagc-lp-thresh-increment-time 1, //fagc_lp_thresh_increment_steps *** adi,fagc-lp-thresh-increment-steps /* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */ 1, //fagc_lock_level_lmt_gain_increase_en *** adi,fagc-lock-level-lmt-gain-increase-enable 5, //fagc_lock_level_gain_increase_upper_limit *** adi,fagc-lock-level-gain-increase-upper-limit /* Fast AGC - Peak Detectors and Final Settling */ 1, //fagc_lpf_final_settling_steps *** adi,fagc-lpf-final-settling-steps 1, //fagc_lmt_final_settling_steps *** adi,fagc-lmt-final-settling-steps 3, //fagc_final_overrange_count *** adi,fagc-final-overrange-count /* Fast AGC - Final Power Test */ 0, //fagc_gain_increase_after_gain_lock_en *** adi,fagc-gain-increase-after-gain-lock-enable /* Fast AGC - Unlocking the Gain */ 0, //fagc_gain_index_type_after_exit_rx_mode *** adi,fagc-gain-index-type-after-exit-rx-mode 1, //fagc_use_last_lock_level_for_set_gain_en *** adi,fagc-use-last-lock-level-for-set-gain-enable 1, //fagc_rst_gla_stronger_sig_thresh_exceeded_en *** adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable 5, //fagc_optimized_gain_offset *** adi,fagc-optimized-gain-offset 10, //fagc_rst_gla_stronger_sig_thresh_above_ll *** adi,fagc-rst-gla-stronger-sig-thresh-above-ll 1, //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en *** adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable 1, //fagc_rst_gla_engergy_lost_goto_optim_gain_en *** adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable 10, //fagc_rst_gla_engergy_lost_sig_thresh_below_ll *** adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll 8, //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt *** adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt 1, //fagc_rst_gla_large_adc_overload_en *** adi,fagc-rst-gla-large-adc-overload-enable 1, //fagc_rst_gla_large_lmt_overload_en *** adi,fagc-rst-gla-large-lmt-overload-enable 0, //fagc_rst_gla_en_agc_pulled_high_en *** adi,fagc-rst-gla-en-agc-pulled-high-enable 0, //fagc_rst_gla_if_en_agc_pulled_high_mode *** adi,fagc-rst-gla-if-en-agc-pulled-high-mode 64, //fagc_power_measurement_duration_in_state5 *** adi,fagc-power-measurement-duration-in-state5 /* RSSI Control */ 1, //rssi_delay *** adi,rssi-delay 1000, //rssi_duration *** adi,rssi-duration 3, //rssi_restart_mode *** adi,rssi-restart-mode 0, //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable 1, //rssi_wait *** adi,rssi-wait /* Aux ADC Control */ 256, //aux_adc_decimation *** adi,aux-adc-decimation 40000000UL, //aux_adc_rate *** adi,aux-adc-rate /* AuxDAC Control */ 1, //aux_dac_manual_mode_enable *** adi,aux-dac-manual-mode-enable 0, //aux_dac1_default_value_mV *** adi,aux-dac1-default-value-mV 0, //aux_dac1_active_in_rx_enable *** adi,aux-dac1-active-in-rx-enable 0, //aux_dac1_active_in_tx_enable *** adi,aux-dac1-active-in-tx-enable 0, //aux_dac1_active_in_alert_enable *** adi,aux-dac1-active-in-alert-enable 0, //aux_dac1_rx_delay_us *** adi,aux-dac1-rx-delay-us 0, //aux_dac1_tx_delay_us *** adi,aux-dac1-tx-delay-us 0, //aux_dac2_default_value_mV *** adi,aux-dac2-default-value-mV 0, //aux_dac2_active_in_rx_enable *** adi,aux-dac2-active-in-rx-enable 0, //aux_dac2_active_in_tx_enable *** adi,aux-dac2-active-in-tx-enable 0, //aux_dac2_active_in_alert_enable *** adi,aux-dac2-active-in-alert-enable 0, //aux_dac2_rx_delay_us *** adi,aux-dac2-rx-delay-us 0, //aux_dac2_tx_delay_us *** adi,aux-dac2-tx-delay-us /* Temperature Sensor Control */ 256, //temp_sense_decimation *** adi,temp-sense-decimation 1000, //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms 0xCE, //temp_sense_offset_signed *** adi,temp-sense-offset-signed 1, //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable /* Control Out Setup */ 0xFF, //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask 0, //ctrl_outs_index *** adi,ctrl-outs-index /* External LNA Control */ 0, //elna_settling_delay_ns *** adi,elna-settling-delay-ns 0, //elna_gain_mdB *** adi,elna-gain-mdB 0, //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB 0, //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable 0, //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable 0, //elna_gaintable_all_index_enable *** adi,elna-gaintable-all-index-enable /* Digital Interface Control */ 0,//2,//0, //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode 0, //digital_interface_tune_fir_disable *** adi,digital-interface-tune-fir-disable 1, //pp_tx_swap_enable *** adi,pp-tx-swap-enable 1, //pp_rx_swap_enable *** adi,pp-rx-swap-enable 0, //tx_channel_swap_enable *** adi,tx-channel-swap-enable 0, //rx_channel_swap_enable *** adi,rx-channel-swap-enable 1, //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable 0, //two_t_two_r_timing_enable *** adi,2t2r-timing-enable 0, //invert_data_bus_enable *** adi,invert-data-bus-enable 0, //invert_data_clk_enable *** adi,invert-data-clk-enable 0, //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable 0, //invert_rx_frame_enable *** adi,invert-rx-frame-enable 0, //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable 0, //swap_ports_enable *** adi,swap-ports-enable 0, //single_data_rate_enable *** adi,single-data-rate-enable 1, //lvds_mode_enable *** adi,lvds-mode-enable 0, //half_duplex_mode_enable *** adi,half-duplex-mode-enable 0, //single_port_mode_enable *** adi,single-port-mode-enable 0, //full_port_enable *** adi,full-port-enable 0, //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable 0, //delay_rx_data *** adi,delay-rx-data 0, //rx_data_clock_delay *** adi,rx-data-clock-delay 4, //rx_data_delay *** adi,rx-data-delay 7, //tx_fb_clock_delay *** adi,tx-fb-clock-delay 0, //tx_data_delay *** adi,tx-data-delay #ifdef ALTERA_PLATFORM 300, //lvds_bias_mV *** adi,lvds-bias-mV #else 150, //lvds_bias_mV *** adi,lvds-bias-mV #endif 1, //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable 0, //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable 0xFF, //lvds_invert1_control *** adi,lvds-invert1-control 0x0F, //lvds_invert2_control *** adi,lvds-invert2-control /* GPO Control */ 0, //gpo0_inactive_state_high_enable *** adi,gpo0-inactive-state-high-enable 0, //gpo1_inactive_state_high_enable *** adi,gpo1-inactive-state-high-enable 0, //gpo2_inactive_state_high_enable *** adi,gpo2-inactive-state-high-enable 0, //gpo3_inactive_state_high_enable *** adi,gpo3-inactive-state-high-enable 0, //gpo0_slave_rx_enable *** adi,gpo0-slave-rx-enable 0, //gpo0_slave_tx_enable *** adi,gpo0-slave-tx-enable 0, //gpo1_slave_rx_enable *** adi,gpo1-slave-rx-enable 0, //gpo1_slave_tx_enable *** adi,gpo1-slave-tx-enable 0, //gpo2_slave_rx_enable *** adi,gpo2-slave-rx-enable 0, //gpo2_slave_tx_enable *** adi,gpo2-slave-tx-enable 0, //gpo3_slave_rx_enable *** adi,gpo3-slave-rx-enable 0, //gpo3_slave_tx_enable *** adi,gpo3-slave-tx-enable 0, //gpo0_rx_delay_us *** adi,gpo0-rx-delay-us 0, //gpo0_tx_delay_us *** adi,gpo0-tx-delay-us 0, //gpo1_rx_delay_us *** adi,gpo1-rx-delay-us 0, //gpo1_tx_delay_us *** adi,gpo1-tx-delay-us 0, //gpo2_rx_delay_us *** adi,gpo2-rx-delay-us 0, //gpo2_tx_delay_us *** adi,gpo2-tx-delay-us 0, //gpo3_rx_delay_us *** adi,gpo3-rx-delay-us 0, //gpo3_tx_delay_us *** adi,gpo3-tx-delay-us /* Tx Monitor Control */ 37000, //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh 0, //low_gain_dB *** adi,txmon-low-gain 24, //high_gain_dB *** adi,txmon-high-gain 0, //tx_mon_track_en *** adi,txmon-dc-tracking-enable 0, //one_shot_mode_en *** adi,txmon-one-shot-mode-enable 511, //tx_mon_delay *** adi,txmon-delay 8192, //tx_mon_duration *** adi,txmon-duration 2, //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain 2, //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain 48, //tx1_mon_lo_cm *** adi,txmon-1-lo-cm 48, //tx2_mon_lo_cm *** adi,txmon-2-lo-cm /* GPIO definitions */ -1, //gpio_resetb *** reset-gpios /* MCS Sync */ -1, //gpio_sync *** sync-gpios -1, //gpio_cal_sw1 *** cal-sw1-gpios -1, //gpio_cal_sw2 *** cal-sw2-gpios /* External LO clocks */ NULL, //(*ad9361_rfpll_ext_recalc_rate)() NULL, //(*ad9361_rfpll_ext_round_rate)() NULL //(*ad9361_rfpll_ext_set_rate)() }; /*AD9361_RXFIRConfig rx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 3, // rx 0, // rx_gain 1, // rx_dec {-4, -6, -37, 35, 186, 86, -284, -315, 107, 219, -4, 271, 558, -307, -1182, -356, 658, 157, 207, 1648, 790, -2525, -2553, 748, 865, -476, 3737, 6560, -3583, -14731, -5278, 14819, 14819, -5278, -14731, -3583, 6560, 3737, -476, 865, 748, -2553, -2525, 790, 1648, 207, 157, 658, -356, -1182, -307, 558, 271, -4, 219, 107, -315, -284, 86, 186, 35, -37, -6, -4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // rx_coef[128] 64, // rx_coef_size {0, 0, 0, 0, 0, 0}, //rx_path_clks[6] 0 // rx_bandwidth };*/ AD9361_RXFIRConfig rx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 3, // rx -6,//0, // rx_gain 2,//1,//2, // rx_dec //{70,408,1071,1658,1335,-170,-1704,-1373,1077,2998,1213,-3542,-5574,627,13584,24378,24378,13584,627,-5574,-3542,1213,2998,1077,-1373,-1704,-170,1335,1658,1071,408,70,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, //{340,468,-408,-6,577,-846,406,676,-1673,1567,157,-2784,4305,-2210,-4932,21291,21291,-4932,-2210,4305,-2784,157,1567,-1673,676,406,-846,577,-6,-408,468,340,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, //DVBS2 Mod Data {-18,-14,21,119,206,199,50,-130,-170,1,213,211,-61,-324,-240,174,467,232,-359,-628,-153,631,784,-40,-1006,-897,404,1498,909,-1031,-2144,-725,2124,3074,118,-4401,-4971,2029,14037,23383,23383,14037,2029,-4971,-4401,118,3074,2124,-725,-2144,-1031,909,1498,404,-897,-1006,-40,784,631,-153,-628,-359,232,467,174,-240,-324,-61,211,213,1,-170,-130,50,199,206,119,21,-14,-18,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 128,//128,//64, // rx_coef_size {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},//{0, 0, 0, 0, 0, 0}, //rx_path_clks[6] 3362055 // rx_bandwidth }; /*AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 3, // tx -6, // tx_gain 1, // tx_int {-4, -6, -37, 35, 186, 86, -284, -315, 107, 219, -4, 271, 558, -307, -1182, -356, 658, 157, 207, 1648, 790, -2525, -2553, 748, 865, -476, 3737, 6560, -3583, -14731, -5278, 14819, 14819, -5278, -14731, -3583, 6560, 3737, -476, 865, 748, -2553, -2525, 790, 1648, 207, 157, 658, -356, -1182, -307, 558, 271, -4, 219, 107, -315, -284, 86, 186, 35, -37, -6, -4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // tx_coef[128] 64, // tx_coef_size {0, 0, 0, 0, 0, 0}, // tx_path_clks[6] 0 // tx_bandwidth };*/ AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 3, // tx 0,//0, // tx_gain 2,//1,//2 // tx_int //{-8,-26,19,264,625,553,-358,-1236,-404,1875,2222,-1631,-5440,-1129,12640,25564,25564,12640,-1129,-5440,-1631,2222,1875,-404,-1236,-358,553,625,264,19,-26,-8,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, //DVBS2 Mod Data //{313,432,-346,-4,492,-731,364,562,-1432,1372,77,-2343,3749,-2133,-3769,20303,20303,-3769,-2133,3749,-2343,77,1372,-1432,562,364,-731,492,-4,-346,432,313,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, //{82,423,1069,1606,1262,-181,-1597,-1236,1063,2780,1014,-3413,-5103,1035,13477,23761,23761,13477,1035,-5103,-3413,1014,2780,1063,-1236,-1597,-181,1262,1606,1069,423,82,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, //{1,-6,-28,-62,-80,-56,11,68,54,-29,-98,-61,64,142,59,-122,-195,-35,210,246,-26,-329,-280,141,476,273,-326,-636,-193,595,786,3,-957,-889,351,1424,890,-953,-2027,-696,1997,2886,76,-4178,-4612,2199,13771,22755,22755,13771,2199,-4612,-4178,76,2886,1997,-696,-2027,-953,890,1424,351,-889,-957,3,786,595,-193,-636,-326,273,476,141,-280,-329,-26,246,210,-35,-195,-122,59,142,64,-61,-98,-29,54,68,11,-56,-80,-62,-28,-6,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, {0,-1,-4,-8,-10,-5,5,12,6,-10,-19,-6,19,28,2,-35,-37,8,57,45,-30,-86,-44,66,118,28,-120,-146,12,191,160,-85,-273,-145,197,353,83,-348,-412,44,531,423,-253,-730,-353,555,918,159,-958,-1052,211,1472,1078,-840,-2125,-900,1920,3034,290,-4144,-4814,1970,13765,22989,22989,13765,1970,-4814,-4144,290,3034,1920,-900,-2125,-840,1078,1472,211,-1052,-958,159,918,555,-353,-730,-253,423,531,44,-412,-348,83,353,197,-145,-273,-85,160,191,12,-146,-120,28,118,66,-44,-86,-30,45,57,8,-37,-35,2,28,19,-6,-19,-10,6,12,5,-5,-10,-8,-4,-1,0}, 128,//64,//128,// 64, // tx_coef_size {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000}, //{0, 0, 0, 0, 0, 0}, // tx_path_clks[6] 3362055 // tx_bandwidth }; struct AD9361_TXFIRConfig *t1; struct ad9361_rf_phy *ad9361_phy; struct ad9361_rf_phy *phy1; #ifdef FMCOMMS5 struct ad9361_rf_phy *ad9361_phy_b; #endif /***************************************************************************//** * @brief main *******************************************************************************/ int main(void) { #ifdef XILINX_PLATFORM Xil_ICacheEnable(); Xil_DCacheEnable(); #endif #ifdef ALTERA_PLATFORM if (altera_bridge_init()) { printf("Altera Bridge Init Error!\n"); return -1; } #endif // NOTE: The user has to choose the GPIO numbers according to desired // carrier board. default_init_param.gpio_resetb = GPIO_RESET_PIN; #ifdef FMCOMMS5 default_init_param.gpio_sync = GPIO_SYNC_PIN; default_init_param.gpio_cal_sw1 = GPIO_CAL_SW1_PIN; default_init_param.gpio_cal_sw2 = GPIO_CAL_SW2_PIN; default_init_param.rx1rx2_phase_inversion_en = 1; #else default_init_param.gpio_sync = -1; default_init_param.gpio_cal_sw1 = -1; default_init_param.gpio_cal_sw2 = -1; #endif #ifdef LINUX_PLATFORM gpio_init(default_init_param.gpio_resetb); #else gpio_init(GPIO_DEVICE_ID); #endif gpio_direction(default_init_param.gpio_resetb, 1); spi_init(SPI_DEVICE_ID, 1, 0); if (AD9364_DEVICE) default_init_param.dev_sel = ID_AD9364; if (AD9363A_DEVICE) default_init_param.dev_sel = ID_AD9363A; #if defined FMCOMMS5 || defined ADI_RF_SOM || defined ADI_RF_SOM_CMOS default_init_param.xo_disable_use_ext_refclk_enable = 1; #endif #ifdef ADI_RF_SOM_CMOS default_init_param.swap_ports_enable = 1; default_init_param.lvds_mode_enable = 0; default_init_param.lvds_rx_onchip_termination_enable = 0; default_init_param.full_port_enable = 1; default_init_param.digital_interface_tune_fir_disable = 1; #endif ad9361_init(&ad9361_phy, &default_init_param); //ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config); //ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config); //////////////////////////////////////////////////////////////////////////////////////////////////// //Added by Mable ad9361_trx_load_enable_fir(ad9361_phy, rx_fir_config, tx_fir_config) ; fn1=ad9361_get_tx_fir_en_dis(phy1,en_dis_fir); fn2=ad9361_get_tx_fir_config( phy1, tx_ch, t1); printf("%d %d : fn1,fn2\n",fn1,fn2); ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #ifdef FMCOMMS5 #ifdef LINUX_PLATFORM gpio_init(default_init_param.gpio_sync); #endif gpio_direction(default_init_param.gpio_sync, 1); default_init_param.id_no = 1; default_init_param.gpio_resetb = GPIO_RESET_PIN_2; #ifdef LINUX_PLATFORM gpio_init(default_init_param.gpio_resetb); #endif default_init_param.gpio_sync = -1; default_init_param.gpio_cal_sw1 = -1; default_init_param.gpio_cal_sw2 = -1; default_init_param.rx_synthesizer_frequency_hz = 2300000000UL; default_init_param.tx_synthesizer_frequency_hz = 2300000000UL; gpio_direction(default_init_param.gpio_resetb, 1); ad9361_init(&ad9361_phy_b, &default_init_param); ad9361_set_tx_fir_config(ad9361_phy_b, tx_fir_config); ad9361_set_rx_fir_config(ad9361_phy_b, rx_fir_config); #endif #ifndef AXI_ADC_NOT_PRESENT #if defined XILINX_PLATFORM || defined LINUX_PLATFORM || defined ALTERA_PLATFORM #ifdef DAC_DMA_EXAMPLE #ifdef FMCOMMS5 dac_init(ad9361_phy_b, DATA_SEL_DMA, 0); #endif dac_init(ad9361_phy, DATA_SEL_DMA, 1); #else #ifdef FMCOMMS5 dac_init(ad9361_phy_b, DATA_SEL_DDS, 0); #endif dac_init(ad9361_phy, DATA_SEL_DDS, 1); #endif #endif #endif #ifdef FMCOMMS5 ad9361_do_mcs(ad9361_phy, ad9361_phy_b); #endif /* #ifndef AXI_ADC_NOT_PRESENT #if (defined XILINX_PLATFORM || defined ALTERA_PLATFORM) && defined ADC_DMA_EXAMPLE // NOTE: To prevent unwanted data loss, it's recommended to invalidate // cache after each adc_capture() call, keeping in mind that the // size of the capture and the start address must be alinged to the size // of the cache line. mdelay(1000); adc_capture(16384, ADC_DDR_BASEADDR); #ifdef XILINX_PLATFORM #ifdef FMCOMMS5 Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384 * 16); #else Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, ad9361_phy->pdata->rx2tx2 ? 16384 * 8 : 16384 * 4); #endif #endif #endif #endif */ #ifdef CONSOLE_COMMANDS get_help(NULL, 0); while(1) { console_get_command(received_cmd); invalid_cmd = 0; for(cmd = 0; cmd < cmd_no; cmd++) { param_no = 0; cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name, param, ¶m_no); if(cmd_type == UNKNOWN_CMD) { invalid_cmd++; } else { cmd_list[cmd].function(param, param_no); } } if(invalid_cmd == cmd_no) { console_print("Invalid command!\n"); } } #endif printf("Done.\n"); #ifdef TDD_SWITCH_STATE_EXAMPLE uint32_t ensm_mode; if (!ad9361_phy->pdata->fdd) { if (ad9361_phy->pdata->ensm_pin_ctrl) { gpio_direction(GPIO_ENABLE_PIN, 1); gpio_direction(GPIO_TXNRX_PIN, 1); gpio_set_value(GPIO_ENABLE_PIN, 0); gpio_set_value(GPIO_TXNRX_PIN, 0); udelay(10); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX control - Alert: %s\n", ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error"); mdelay(1000); if (ad9361_phy->pdata->ensm_pin_pulse_mode) { while(1) { gpio_set_value(GPIO_TXNRX_PIN, 0); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 1); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 0); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX Pulse control - RX: %s\n", ensm_mode == ENSM_MODE_RX ? "OK" : "Error"); mdelay(1000); gpio_set_value(GPIO_ENABLE_PIN, 1); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 0); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX Pulse control - Alert: %s\n", ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error"); mdelay(1000); gpio_set_value(GPIO_TXNRX_PIN, 1); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 1); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 0); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX Pulse control - TX: %s\n", ensm_mode == ENSM_MODE_TX ? "OK" : "Error"); mdelay(1000); gpio_set_value(GPIO_ENABLE_PIN, 1); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 0); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX Pulse control - Alert: %s\n", ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error"); mdelay(1000); } } else { while(1) { gpio_set_value(GPIO_TXNRX_PIN, 0); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 1); udelay(10); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX control - RX: %s\n", ensm_mode == ENSM_MODE_RX ? "OK" : "Error"); mdelay(1000); gpio_set_value(GPIO_ENABLE_PIN, 0); udelay(10); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX control - Alert: %s\n", ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error"); mdelay(1000); gpio_set_value(GPIO_TXNRX_PIN, 1); udelay(10); gpio_set_value(GPIO_ENABLE_PIN, 1); udelay(10); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX control - TX: %s\n", ensm_mode == ENSM_MODE_TX ? "OK" : "Error"); mdelay(1000); gpio_set_value(GPIO_ENABLE_PIN, 0); udelay(10); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("TXNRX control - Alert: %s\n", ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error"); mdelay(1000); } } } else { while(1) { ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_RX); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("SPI control - RX: %s\n", ensm_mode == ENSM_MODE_RX ? "OK" : "Error"); mdelay(1000); ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("SPI control - Alert: %s\n", ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error"); mdelay(1000); ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_TX); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("SPI control - TX: %s\n", ensm_mode == ENSM_MODE_TX ? "OK" : "Error"); mdelay(1000); ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT); ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode); printf("SPI control - Alert: %s\n", ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error"); mdelay(1000); } } } #endif #ifdef XILINX_PLATFORM Xil_DCacheDisable(); Xil_ICacheDisable(); #endif #ifdef ALTERA_PLATFORM if (altera_bridge_uninit()) { printf("Altera Bridge Uninit Error!\n"); return -1; } #endif return 0; }
After making these changes, initialization error is coming and invalid command print is coming continuously.Please find the attached log.
ad9361_reset: by GPIO ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_setup ad9361_set_dcxo_tune : coarse 7 fine 5900 ad9361_set_trx_clock_chain ad9361_set_trx_clock_chain: 0 0 0 0 0 0 ad9361_set_trx_clock_chain: 0 0 0 0 0 0 ad9361_bbpll_set_rate: Rate 715000000 Hz Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 715000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_round_rate: divide by zero ad9361_clk_factor_set_rate: Rate 89375000 Hz Parent Rate 89375000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_dig_tune: freq 0 flags 0x10 ad9361_set_tx_atten : attenuation 89750 mdB tx1=1 tx2=1 ad9361_bist_loopback: mode 0 ad9361_bist_prbs: mode 2 Device is in 0 state, forcing to 5 Device is in 5 state, forcing to a Failed to restore state Nothing to do, device is already in 5 state Device is in 5 state, forcing to a Failed to restore state SAMPL CLK: 89375000 tuning: RX 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:# # # # # # # # # # # # # # # # 1:# # # # # # # # # # # # # # # # ad9361_dig_tune_delay: Tuning RX FAILED! ad9361_bist_loopback: mode 0 Nothing to do, device is already in 5 state Could not restore to 0 ENSM state ad9361_set_tx_atten : attenuation 0 mdB tx1=1 tx2=1 ad9361_rssi_setup ad9361_auxadc_setup ad9361_rf_port_setup : INPUT_SELECT 0x3 ad9361_pp_port_setup ad9361_auxdac_setup ad9361_auxdac_set DAC1 = 0 mV ad9361_auxdac_set DAC2 = 0 mV ad9361_auxadc_setup ad9361_ctrl_outs_setup ad9361_gpo_setup ad9361_set_ref_clk_cycles : ref_clk_hz 40000000 ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 40000000 Hz ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 40000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_txrx_synth_cp_calib : ref_clk_hz 80000000 : is_tx 0 ad9361_txrx_synth_cp_calib : ref_clk_hz 80000000 : is_tx 1 ad9361_rfpll_int_round_rate: Rate 725000000 Hz ad9361_rfpll_int_round_rate: Rate 725000000 Hz ad9361_rfpll_int_set_rate: RX Rate 725000000 Hz Parent Rate 80000000 Hz ad9361_fastlock_prepare: RX Profile 0: Un-Prepare ad9361_rfpll_vco_init : vco_freq 11600000000 : ref_clk 80000000 : range 2 ad9361_rfpll_vco_init : freq 11588 MHz : index 3 ad9361_load_gt: frequency 1450000000 ad9361_load_gt: frequency 1450000000 (band 1) ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_round_rate: Rate 725000000 Hz ad9361_rfpll_int_set_rate: TX Rate 725000000 Hz Parent Rate 80000000 Hz ad9361_fastlock_prepare: TX Profile 0: Un-Prepare ad9361_rfpll_vco_init : vco_freq 11600000000 : ref_clk 80000000 : range 2 ad9361_rfpll_vco_init : freq 11588 MHz : index 3 ad9361_rfpll_vco_init : vco_freq 11600000000 : ref_clk 80000000 : range 2 ad9361_rfpll_vco_init : freq 11588 MHz : index 3 ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_clk_mux_set_parent: index 0 Nothing to do, device is already in 5 state ad9361_trx_ext_lo_control : RX state 0 ad9361_clk_mux_set_parent: index 0 Nothing to do, device is already in 5 state ad9361_trx_ext_lo_control : TX state 0 ad9361_load_mixer_gm_subtable ad9361_gc_setup ad9361_rx_bb_analog_filter_calib : rx_bb_bw 0 bbpll_freq 715000000 ad9361_run_calibration: CAL Mask 0x80 ad9361_tx_bb_analog_filter_calib : tx_bb_bw 0 bbpll_freq 715000000 ad9361_run_calibration: CAL Mask 0x40 ad9361_rx_tia_calib : bb_bw_Hz 0 ad9361_tx_bb_second_filter_calib : tx_bb_bw 0 ad9361_rx_adc_setup : BBBW 199790 : ADCfreq 89375000 c3_msb 0x30 : c3_lsb 0xD : r2346 0x4 : invrc_tconst_1e6 1023801, sqrt_inv_rc_tconst_1e3 1011 scaled_adc_clk_1e6 139648, inv_scaled_adc_clk_1e3 7161 tmp_1e3 1016, sqrt_term_1e3 373, min_sqrt_term_1e3 747 ad9361_bb_dc_offset_calib ad9361_run_calibration: CAL Mask 0x1 ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz ad9361_rf_dc_offset_calib : rx_freq 1450000000 ad9361_run_calibration: CAL Mask 0x2 Calibration TIMEOUT (0x16, 0x2) ad9361_init : AD936x initialization error 2 : set filter config tx_fir_int! ad9361_load_fir_filter_coef: TAPS 128, gain 0, dest 3 Device is in 3 state, forcing to 5 Failed to restore state Could not restore to 3 ENSM state 2 : rx_fir_dec! ad9361_load_fir_filter_coef: TAPS 128, gain -6, dest 131 Device is in 3 state, forcing to 5 Failed to restore state Could not restore to 3 ENSM state ad9361_validate_enable_fir: TX FIR EN=1/TAPS128/INT2, RX FIR EN=1/TAPS128/DEC2 ad9361_set_trx_clock_chain ad9361_set_trx_clock_chain: 1024000000 64000000 32000000 16000000 8000000 4000000 ad9361_set_trx_clock_chain: 1024000000 64000000 32000000 16000000 8000000 4000000 ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 277133312 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_rfpll_int_recalc_rate: Parent Rate 0 Hz ad9361_dig_tune: freq 0 flags 0x10 ad9361_set_tx_atten : attenuation 89750 mdB tx1=1 tx2=1 ad9361_bist_loopback: mode 0 ad9361_bist_prbs: mode 2 Device is in 3 state, forcing to 5 Failed to restore state Device is in 3 state, forcing to a Failed to restore state Device is in 3 state, forcing to 5 Failed to restore state Device is in 3 state, forcing to a Failed to restore state SAMPL CLK: 0 tuning: RX 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: 0:# # # # # # # # # # # # # # # # 1:# # # # # # # # # # # # # # # # ad9361_dig_tune_delay: Tuning RX FAILED! ad9361_bist_loopback: mode -1342177277 Device is in 3 state, forcing to 5 Failed to restore state Could not restore to 3 ENSM state ad9361_set_tx_atten : attenuation 0 mdB tx1=1 tx2=1 ad9361_rssi_setup ad9361_auxadc_setup ad9361_tracking_control : bbdc_track=0, rfdc_track=0, rxquad_track=0 Device is in 3 state, forcing to 5 Failed to restore state __ad9361_update_rf_bandwidth: 3362055 3362055 ad9361_rx_bb_analog_filter_calib : rx_bb_bw 1681027 bbpll_freq 0 ad9361_run_calibration: CAL Mask 0x80 ad9361_tx_bb_analog_filter_calib : tx_bb_bw 1681027 bbpll_freq 0 ad9361_run_calibration: CAL Mask 0x40 ad9361_rx_tia_calib : bb_bw_Hz 1681027 ad9361_tx_bb_second_filter_calib : tx_bb_bw 1681027 ad9361_rx_adc_setup : BBBW 0 : ADCfreq 0 c3_msb 0x0 : c3_lsb 0x0 : r2346 0x1 : invrc_tconst_1e6 4507, sqrt_inv_rc_tconst_1e3 67 scaled_adc_clk_1e6 0, inv_scaled_adc_clk_1e3 0 tmp_1e3 1000, sqrt_term_1e3 0, min_sqrt_term_1e3 0 ad9361_tx_quad_calib : bw_tx 1681027 clkrf 0 clktf 0 Tx NCO frequency: 0 (BW/4: 420256) txnco_word 0 ad9361_run_calibration: CAL Mask 0x10 LO leakage: 1 Quadrature Calibration: 1 : rx_phase 14 ad9361_tracking_control : bbdc_track=176, rfdc_track=0, rxquad_track=164 Could not restore to 3 ENSM state 2 : get filter config rx_fir_int! 0 0 : fn1,fn2 Available commands: help? - Displays all available commands. register? - Gets the specified register value. tx_lo_freq? - Gets current TX LO frequency [MHz]. tx_lo_freq= - Sets the TX LO frequency [MHz]. tx_samp_freq? - Gets current TX sampling frequency [Hz]. tx_samp_freq= - Sets the TX sampling frequency [Hz]. tx_rf_bandwidth? - Gets current TX RF bandwidth [Hz]. tx_rf_bandwidth= - Sets the TX RF bandwidth [Hz]. tx1_attenuation? - Gets current TX1 attenuation [mdB]. tx1_attenuation= - Sets the TX1 attenuation [mdB]. tx2_attenuation? - Gets current TX2 attenuation [mdB]. tx2_attenuation= - Sets the TX2 attenuation [mdB]. tx_fir_en? - Gets current TX FIR state. tx_fir_en= - Sets the TX FIR state. rx_lo_freq? - Gets current RX LO frequency [MHz]. rx_lo_freq= - Sets the RX LO frequency [MHz]. rx_samp_freq? - Gets current RX sampling frequency [Hz]. rx_samp_freq= - Sets the RX sampling frequency [Hz]. rx_rf_bandwidth? - Gets current RX RF bandwidth [Hz]. rx_rf_bandwidth= - Sets the RX RF bandwidth [Hz]. rx1_gc_mode? - Gets current RX1 GC mode. rx1_gc_mode= - Sets the RX1 GC mode. rx2_gc_mode? - Gets current RX2 GC mode. rx2_gc_mode= - Sets the RX2 GC mode. rx1_rf_gain? - Gets current RX1 RF gain. rx1_rf_gain= - Sets the RX1 RF gain. rx2_rf_gain? - Gets current RX2 RF gain. rx2_rf_gain= - Sets the RX2 RF gain. rx_fir_en? - Gets current RX FIR state. rx_fir_en= - Sets the RX FIR state. dds_tx1_tone1_freq? - Gets current DDS TX1 Tone 1 frequency [Hz]. dds_tx1_tone1_freq= - Sets the DDS TX1 Tone 1 frequency [Hz]. dds_tx1_tone2_freq? - Gets current DDS TX1 Tone 2 frequency [Hz]. dds_tx1_tone2_freq= - Sets the DDS TX1 Tone 2 frequency [Hz]. dds_tx1_tone1_phase? - Gets current DDS TX1 Tone 1 phase [degrees]. dds_tx1_tone1_phase= - Sets the DDS TX1 Tone 1 phase [degrees]. dds_tx1_tone2_phase? - Gets current DDS TX1 Tone 2 phase [degrees]. dds_tx1_tone2_phase= - Sets the DDS TX1 Tone 2 phase [degrees]. dds_tx1_tone1_scale? - Gets current DDS TX1 Tone 1 scale. dds_tx1_tone1_scale= - Sets the DDS TX1 Tone 1 scale. dds_tx1_tone2_scale? - Gets current DDS TX1 Tone 2 scale. dds_tx1_tone2_scale= - Sets the DDS TX1 Tone 2 scale. dds_tx2_tone1_freq? - Gets current DDS TX2 Tone 1 frequency [Hz]. dds_tx2_tone1_freq= - Sets the DDS TX2 Tone 1 frequency [Hz]. dds_tx2_tone2_freq? - Gets current DDS TX2 Tone 2 frequency [Hz]. dds_tx2_tone2_freq= - Sets the DDS TX2 Tone 2 frequency [Hz]. dds_tx2_tone1_phase? - Gets current DDS TX2 Tone 1 phase [degrees]. dds_tx2_tone1_phase= - Sets the DDS TX2 Tone 1 phase [degrees]. dds_tx2_tone2_phase? - Gets current DDS TX2 Tone 2 phase [degrees]. dds_tx2_tone2_phase= - Sets the DDS TX2 Tone 2 phase [degrees]. dds_tx2_tone1_scale? - Gets current DDS TX2 Tone 1 scale. dds_tx2_tone1_scale= - Sets the DDS TX2 Tone 1 scale. dds_tx2_tone2_scale? - Gets current DDS TX2 Tone 2 scale. dds_tx2_tone2_scale= - Sets the DDS TX2 Tone 2 scale. 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Waiting for the response from your side.
Thanks,
Mable George
You can't initialize the part to a 0 Hz sampling rate.
Don't modify anything to default_init_param - generate your own FIR configuration files and load/enable them using ad9361_trx_load_enable_fir().
Dragos
If we don't modify anything in default_init_param , where we can set rx_synthesizer_frequency_hz,tx_synthesizer_frequency_hz,tx_attenuation_mdB?
As per your suggestion without modifying anything in default_init_param and loaded using ad9361_trx_load_enable_fir(). Instead of taking tx_samp_freq,rx_samp_freq, etc from FIR filter structure it is taking from default_init_param.
Please see the attached filter structures and provide the feedback.
AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 3, // tx 0, // tx_gain 2,// tx_int {0,-1,-4,-8,-10,-5,5,12,6,-10,-19,-6,19,28,2,-35,-37,8,57,45,-30,-86,-44,66,118,28,-120,-146,12,191,160,-85,-273,-145,197,353,83,-348,-412,44,531,423,-253,-730,-353,555,918,159,-958,-1052,211,1472,1078,-840,-2125,-900,1920,3034,290,-4144,-4814,1970,13765,22989,22989,13765,1970,-4814,-4144,290,3034,1920,-900,-2125,-840,1078,1472,211,-1052,-958,159,918,555,-353,-730,-253,423,531,44,-412,-348,83,353,197,-145,-273,-85,160,191,12,-146,-120,28,118,66,-44,-86,-30,45,57,8,-37,-35,2,28,19,-6,-19,-10,6,12,5,-5,-10,-8,-4,-1,0}, 128, // tx_coef_size {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000}, // tx_path_clks[6] 3362055 // tx_bandwidth }; AD9361_RXFIRConfig rx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 3, // rx -6,// rx_gain 2, // rx_dec {-18,-14,21,119,206,199,50,-130,-170,1,213,211,-61,-324,-240,174,467,232,-359,-628,-153,631,784,-40,-1006,-897,404,1498,909,-1031,-2144,-725,2124,3074,118,-4401,-4971,2029,14037,23383,23383,14037,2029,-4971,-4401,118,3074,2124,-725,-2144,-1031,909,1498,404,-897,-1006,-40,784,631,-153,-628,-359,232,467,174,-240,-324,-61,211,213,1,-170,-130,50,199,206,119,21,-14,-18,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 128, // rx_coef_size {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000}, //rx_path_clks[6] 3362055 // rx_bandwidth };
mgeorge@cdot.in said:If we don't modify anything in default_init_param , where we can set rx_synthesizer_frequency_hz,tx_synthesizer_frequency_hz,tx_attenuation_mdB?
You need to use the regular driver API to do that.
Problem got resolved. Thanks for the help.