AD9361 TXFIR int 0 RXFIR dec 0 mode Highest OSR

Please use the filter wizard tool to create a custom profile. 

Please refer to bellow posts,

https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88114/ad9361_dig_tune-tuning-failed-when-using-no-os-drivers

https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88110/fir-structure-parameter-initialization-error

we used  this function in main.c ad9361_trx_load_enable_fir(ad9361_phy, rx_fir_config, tx_fir_config)" ,and still we got same error "ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit.

Hi, i used fir coefficients in tx_fir and rx_fir structures in main.c, still i am  facing same error as earlier.here iam attaching screenshots for tx_fir , rx_fir structures and error message.

Hi,

Waiting for suggestions from your side.

Hi,

I'm doubting that whatever I assigned for initializing AD9361 has reflected in actual hardware or not?  I tried to read back fir filter parameters using ad9361_get_tx_fir_config. But I was not getting back the same values which I assigned.

Along with that, I'm still facing the error.ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSR. ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit".

Hope you will provide more debugging option and helpful solutions .

what is the version of SW and FPGA files that you are using? Have you modified the HDK files?

mhennerich can you please comment on this.

Hi,

Thanks for the reply.

Vesion of files are hdl-hdl_2017_r1 and no-OS-master.

I modified the block design.

Initially I was working on KC705+FMCOMMS3 board.Data has transmitted and received properly in that. Now,I'm facing these issues in our custom board with Kintex-7 FPGA(xc7k160tffg676-1) and FMCOMMS3 board. Here DDR is not there in Custom board. So I have modified the block design without DDR and increased sys_ilmb_cntlr_Mem,sys_dlmb_cntlr_Mem to size to 512K. I removed axi_ad9361_dac_dma and axi_ad9361_adc_dma and feeded data through RAM to AXI-AD9361 IP. Then exported the hardware. In SDK heap size is increased to 0x10000 in lscript.ld file. These all are the changes i made.

Expecting suggestions from your side.

Thanks in advance.

Hi,

Thanks for the reply.

Vesion of files are hdl-hdl_2017_r1 and no-OS-master.

I modified the block design.

Initially I was working on KC705+FMCOMMS3 board.Data has transmitted and received properly in that. Now,I'm facing these issues in our custom board with Kintex-7 FPGA(xc7k160tffg676-1) and FMCOMMS3 board. Here DDR is not there in Custom board. So I have modified the block design without DDR and increased sys_ilmb_cntlr_Mem,sys_dlmb_cntlr_Mem to size to 512K. I removed axi_ad9361_dac_dma and axi_ad9361_adc_dma and feeded data through RAM to AXI-AD9361 IP. Then exported the hardware. In SDK heap size is increased to 0x10000 in lscript.ld file. These all are the changes i made.

Expecting suggestions from your side.

Thanks in advance.

Moving to FPGA subspace. Someone here will be able to verify the changes done.

Hi,

Waiting for the reply from your side.

Thanks,

Mable

Hi,

How do you configure/enable the filters? You should use the ad9361_trx_load_enable_fir() API (don't call ad9361_set_rx/tx_fir_en_dis()) - it will enable the filters simultaneously and it will load the coefficients and the frequencies information too - that's mandatory since you can't have different sampling rates on RX and TX.

Thanks,
Dragos

Hi,

Sampling rates for both transmit and receive chain are same.

I tried out thisad9361_trx_load_enable_fir(ad9361_phy, rx_fir_config, tx_fir_config)  function earlier itself.

Still getting same error only.

ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSR

ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit.

What about the changes which I made in block design.All are correct,  right?

Hi,

First of all never modify the rates in the init structure.

Then design a filter for both RX and TX paths. If you load it and then enable it simultaneously there shouldn't be any error.

Can you please provide your entire setup code snippet?

-Michael