AD9361 TXFIR int 0 RXFIR dec 0 mode Highest OSR

mgeorge@cdot.in on Sep 20, 2019

Hi,

These are the inputs given by us for configuring AD9361.

{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

AD9361_TXFIRConfig tx_fir_config = {   // BPF PASSBAND 3/20 fs to 1/4 fs
   1, // tx
   -6, tx_gain
   2 ,//tx_int
{1,-6,-28,-62,-80,-56,11,68,54,-29,-98,-61,64,142,59,-122,-195,-35,210,246,-26,-329,-280,141,476,273,-326,-636,-193,595,786,3,-957,-889,351,1424,890,-953,-2027,-696,1997,2886,76,-4178,-4612,2199,13771,22755,22755,13771,2199,-4612,-4178,76,2886,1997,-696,-2027,-953,890,1424,351,-889,-957,3,786,595,-193,-636,-326,273,476,141,-280,-329,-26,246,210,-35,-195,-122,59,142,64,-61,-98,-29,54,68,11,-56,-80,-62,-28,-6,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
   128, // tx_coef_size
   {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000}, //{0, 0, 0, 0, 0, 0}, // tx_path_clks[6]
   1330000 // tx_bandwidth
};

but we are getting error ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSR
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit".

please give the feedback how to solve thiis error.

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Vinod
Sep 27, 2019 in reply to mgeorge@cdot.in +1 verified
Moving to FPGA subspace. Someone here will be able to verify the changes done.

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0 PVALAVAN

on Sep 20, 2019 9:37 AM over 1 year ago
Please use the filter wizard tool to create a custom profile.

Please refer to bellow posts,

https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88114/ad9361_dig_tune-tuning-failed-when-using-no-os-drivers

https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88110/fir-structure-parameter-initialization-error
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0 mgeorge@cdot.in on Sep 20, 2019 10:59 AM over 1 year ago in reply to PVALAVAN

we used this function in main.c ad9361_trx_load_enable_fir(ad9361_phy, rx_fir_config, tx_fir_config)" ,and still we got same error "ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit.
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0 srimoyi

on Sep 23, 2019 12:11 PM over 1 year ago in reply to mgeorge@cdot.in

6431.ezone1.txt

# Generated with AD9361 Filter Design Wizard 16.1.3
# MATLAB 9.0.0.341360 (R2016a), 23-Sep-2019 11:41:42
# Inputs:
# Data Sample Frequency = 4000000 Hz
TX 3 GAIN 0 INT 2
RX 3 GAIN -6 DEC 2
RTX 1024000000 64000000 32000000 16000000 8000000 4000000
RRX 1024000000 64000000 32000000 16000000 8000000 4000000
BWTX 3362055
BWRX 3362068
0,-18
-1,-14
-4,21
-8,119
-10,206
-5,199
5,50
12,-130
6,-170
-10,1
-19,213
-6,211
19,-61
28,-324
2,-240
-35,174
-37,467
8,232
57,-359
45,-628
-30,-153
-86,631
-44,784
66,-40
118,-1006
28,-897
-120,404
-146,1498
12,909
191,-1031
160,-2144
-85,-725
-273,2124
-145,3074
197,118
353,-4401
83,-4971
-348,2029
-412,14037
44,23383
531,23383
423,14037
-253,2029
-730,-4971
-353,-4401
555,118
918,3074
159,2124
-958,-725
-1052,-2144
211,-1031
1472,909
1078,1498
-840,404
-2125,-897
-900,-1006
1920,-40
3034,784
290,631
-4144,-153
-4814,-628
1970,-359
13765,232
22989,467
22989,174
13765,-240
1970,-324
-4814,-61
-4144,211
290,213
3034,1
1920,-170
-900,-130
-2125,50
-840,199
1078,206
1472,119
211,21
-1052,-14
-958,-18
159,0
918,0
555,0
-353,0
-730,0
-253,0
423,0
531,0
44,0
-412,0
-348,0
83,0
353,0
197,0
-145,0
-273,0
-85,0
160,0
191,0
12,0
-146,0
-120,0
28,0
118,0
66,0
-44,0
-86,0
-30,0
45,0
57,0
8,0
-37,0
-35,0
2,0
28,0
19,0
-6,0
-19,0
-10,0
6,0
12,0
5,0
-5,0
-10,0
-8,0
-4,0
-1,0
0,0

Can you try loading the attached filter file and check. It is created with the same settings as yours.

0 mgeorge@cdot.in on Sep 24, 2019 4:41 AM over 1 year ago in reply to srimoyi

Hi, i used fir coefficients in tx_fir and rx_fir structures in main.c, still i am facing same error as earlier.here iam attaching screenshots for tx_fir , rx_fir structures and error message.
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0 mgeorge@cdot.in on Sep 25, 2019 8:06 AM over 1 year ago in reply to mgeorge@cdot.in

Hi,

Waiting for suggestions from your side.
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0 mgeorge@cdot.in on Sep 27, 2019 4:16 AM over 1 year ago in reply to srimoyi

Hi,

I'm doubting that whatever I assigned for initializing AD9361 has reflected in actual hardware or not? I tried to read back fir filter parameters using ad9361_get_tx_fir_config. But I was not getting back the same values which I assigned.

Along with that, I'm still facing the error.ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSR. ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit".

Hope you will provide more debugging option and helpful solutions .
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0 Vinod

on Sep 27, 2019 6:49 AM over 1 year ago in reply to mgeorge@cdot.in
what is the version of SW and FPGA files that you are using? Have you modified the HDK files?

mhennerich can you please comment on this.
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0 Vinod

on Sep 27, 2019 6:49 AM over 1 year ago in reply to mgeorge@cdot.in
what is the version of SW and FPGA files that you are using? Have you modified the HDK files?

mhennerich can you please comment on this.
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0 mgeorge@cdot.in on Sep 27, 2019 8:47 AM over 1 year ago in reply to Vinod

Hi,

Thanks for the reply.

Vesion of files are hdl-hdl_2017_r1 and no-OS-master.

I modified the block design.

Initially I was working on KC705+FMCOMMS3 board.Data has transmitted and received properly in that. Now,I'm facing these issues in our custom board with Kintex-7 FPGA(xc7k160tffg676-1) and FMCOMMS3 board. Here DDR is not there in Custom board. So I have modified the block design without DDR and increased sys_ilmb_cntlr_Mem,sys_dlmb_cntlr_Mem to size to 512K. I removed axi_ad9361_dac_dma and axi_ad9361_adc_dma and feeded data through RAM to AXI-AD9361 IP. Then exported the hardware. In SDK heap size is increased to 0x10000 in lscript.ld file. These all are the changes i made.

Expecting suggestions from your side.

Thanks in advance.
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+1 Vinod

on Sep 27, 2019 9:51 AM over 1 year ago in reply to mgeorge@cdot.in
Moving to FPGA subspace. Someone here will be able to verify the changes done.
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0 mgeorge@cdot.in on Sep 30, 2019 10:11 AM over 1 year ago in reply to Vinod

Hi,

Waiting for the reply from your side.

Thanks,

Mable
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0 DragosB

on Sep 30, 2019 7:43 PM over 1 year ago in reply to mgeorge@cdot.in
Hi,

How do you configure/enable the filters? You should use the ad9361_trx_load_enable_fir() API (don't call ad9361_set_rx/tx_fir_en_dis()) - it will enable the filters simultaneously and it will load the coefficients and the frequencies information too - that's mandatory since you can't have different sampling rates on RX and TX.

Thanks,
Dragos
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0 mgeorge@cdot.in on Oct 1, 2019 4:13 AM over 1 year ago in reply to DragosB

Hi,

Sampling rates for both transmit and receive chain are same.

I tried out thisad9361_trx_load_enable_fir(ad9361_phy, rx_fir_config, tx_fir_config) function earlier itself.

Still getting same error only.

ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSR

ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit.

What about the changes which I made in block design.All are correct, right?
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