Hi,
These are the inputs given by us for configuring AD9361.
{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs 1, // tx -6, tx_gain 2 ,//tx_int{1,-6,-28,-62,-80,-56,11,68,54,-29,-98,-61,64,142,59,-122,-195,-35,210,246,-26,-329,-280,141,476,273,-326,-636,-193,595,786,3,-957,-889,351,1424,890,-953,-2027,-696,1997,2886,76,-4178,-4612,2199,13771,22755,22755,13771,2199,-4612,-4178,76,2886,1997,-696,-2027,-953,890,1424,351,-889,-957,3,786,595,-193,-636,-326,273,476,141,-280,-329,-26,246,210,-35,-195,-122,59,142,64,-61,-98,-29,54,68,11,-56,-80,-62,-28,-6,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 128, // tx_coef_size {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000}, //{0, 0, 0, 0, 0, 0}, // tx_path_clks[6] 1330000 // tx_bandwidth};
but we are getting error ad9361_calculate_rf_clock_chain: requested rate 4000000 TXFIR int 0 RXFIR dec 0 mode Highest OSRad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit".
please give the feedback how to solve thiis error.
Please use the filter wizard tool to create a custom profile.
Please refer to bellow posts,
https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88114/ad9361_dig_tune-tuning-failed-when-using-no-os-drivers
https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/f/q-a/88110/fir-structure-parameter-initialization-error
we used this function in main.c ad9361_trx_load_enable_fir(ad9361_phy, rx_fir_config, tx_fir_config)" ,and still we got same error "ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit.
Can you please share the profile you have generated from filter wizard tool?
Filter = 2 Phase Equalization = 0 Use AD936x FIR = 1 Fpass = 1.333300e+00 Fstop = 1.666700e+00 Apass = 5.000000e-01 Astop = 80 Param = 0.000000 PLL rate = 1024 Converter = 64 Data rate = 4
Please find the attached document with filter parameters for both transmit and receive .
This is the settings provided in AD9361_Filter_Wizard GUI
One of the observation which I made now is
While setting FIR filter parameters I'm using the function of ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);. That time I'm setting tx_int as 2. But While reading back using fn2=ad9361_get_tx_fir_config( phy1, tx_ch, t1); I'm getting interpolation as 0. What might be the possible reasons for that? Why assigned value is not reflecting ?
How can I verify the other parameters which I used to initialize AD9361 has reflected or not?