AD9371 interfacing with ZCU102

Hi,

We recommend using the latest release, having that uses the 2018.2 Vivado version.
To validate the zcu102 you should find some reference design for this on Xilinx's sites.
The only configuration that I can think of that you have to do, in order to use the ADI reference design is to configure the switches on the board, to boot from the SD card.

Andrei

Hi Andrei,

 Is it possible to get a bit file and elf file to test the basic functionality of the hardware (ZCU102(0432055-05,newer DIMM) and AD9371).If this gets confirmed ,later I will work on the building my own project using the files provided by ADI.

Thanks and Regards 

B MOURYA

Hi,

The 2018_r2 Linux image contains the BOOT.BIN compatible with the newer memory.
https://wiki.analog.com/resources/tools-software/linux-software/embedded_arm_images

Andrei

Hi,

Is it available for NO-OS?

Thanks and Regards 

B MOURYA

Hi,

In no-OS, you will have to manually add the workaround described by Xilinx.
https://www.xilinx.com/support/answers/71961.html

Andrei

Hi,

At this moment, we don't deliver no-OS prebuilt files. For instructions regarding the building of those files, have a look here: https://wiki.analog.com/resources/eval/user-guides/mykonos/no-os-setup and if you need new SODIMM support, check this: https://github.com/analogdevicesinc/wiki-scripts/pull/5 .

Thanks,
Dragos

Hi,

I build the project in vivado 2017.4 using the files provided by ADI.

when I program the device I am getting the following prints in the terminal

please wait .....

WARNING:AD9528_initialize() issues.Possible cause:REF_CLK not connected.

xcvr_calc_cpll_config:Failed to find matching dividers for 491520 KHz rate

xcvr_calc_qpll_config:Failed to find matching dividers for 491520 KHz rate

xcvr_calc_cpll_config:Failed to find matching dividers for 491520 KHz rate

RX_XCVR(GTH4) initialization OK

TX_XCVR(GTH4) initialization OK

RX_OS_XCVR(GTH4) initialization OK

Clock PLL Lock event timed out in MYKONOS_waitForEvent()

I am not connecting any external reference clock (generated profile file by selecting Bypass PLL1 in filter wizard)

generated script files using the profile generated previously using TES (hardware is not connected )

please tell me what will happen if I generate the script files without connecting the hardware

I tried to connect the hardware but I am getting the following error

"The ZYNQ board is disconnected.

Please check your network settings and reboot the platform".

please tell me

1)how to solve this connection issue.

2)In UG-922 pg:281 is telling to insert the SD card for the ZYNQ device for using TES.what is the reason for this

3)The below link says that external ref  clock (30.72 MHz)is required for the TES to work ,Is it correct?

https://ez.analog.com/wide-band-rf-transceivers/tes-gui-and-api-software-ad9371-ad9375/f/q-a/98885/tes-gui-not-connected-to-the-board

4)If external clock is required cumpolsary then we should give only 30.72 MHz or we can give any other frequencies,if we can give then what is the max frequency we can give

Thanks and Regards 

Mourya

Hi,

Sorry for the late reply,
Please use the latest sources from https://github.com/analogdevicesinc/no-OS/tree/master/projects/ad9371

Andrei