I want to control fastlock profiling from FPGA.
I'm using adrv9361-z7035 with linux OS on PS side. I have read in ad9361 reference manual (ug570) that CTRL_IN pins are used to select the desired stored profile. but i'm confused how can i access these pins in hdl design like Micheal suggested here https://ez.analog.com/linux-device-drivers/linux-software-drivers/f/q-a/87329/understanding-ad9361-iiostream-c-example/150200#150200.
I have checked https://github.com/analogdevicesinc/linux_image_ADI-scripts/blob/master/test_tx_fastlock_pinctrl.sh example. I removed the debug messages and sleep command to minimize the delays but still it's timing performance is not stable. selecting 8 stored profile takes 13 u to 70 u seconds and this time is not stable. secondly my fastlock profile changing is dependent on hdl signals so i think i would be better to control fastlock profiles from hdl.
mhennerichcan u help me here.
I've mistakenly moved the thread to Linux Software Drivers, but FPGA Reference Designs section is the right place to be.
See here: https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom/tutorials/frequency_hopping
1. This is dependent on the sample rate as the dwell is based on samples, not time. Note that the transition phase, which is the samples counted during the LO transition before re-enabling the DMA, is fixed in the current design. You will need to configure this also based on your sample rate. This is the "waitSamples" in the "Enable Control" block.
2. See page 24 (bottom) in the UG-570 doc if you want to use both TX and RX fastlock.
Thank you very much. sorry i was away from this work for a week.
1. Inside the FPGA data is the only real concept of time, which is why it is used. 20 was used as an arbitrary number just for the example. However, you will need to measure it for your application and will be based on the sample rate. Generally, you need an oscilloscope to do this accurately or just simply make it larger than 25 us.
2. Yes, see 1.
I have more questions regarding axi_hopper IP.
I just noticed that design build using adi wiki guide has gpio_en_agc port disconnected in main block design. Also, TX attenuation is not working from IIO-OSC. I mean osc is running, other functions are working as expected but T signal does not attenuates when we change attenuation. I also tried to change the TX attenuation from command line using device attributes but attenuation did not appear.
May be this is due to the disconnected port gpio_en_agc. is this disconnection deliberate?
Can u please comment on this
There is no such attribute called attenuation. The attribute is called hardwaregain, which is an output attribute (note that there are 2).
GPIO is only used if you are using pin control for gain control. IIO-Scope only does things through SPI.
Thank you very much
what is the function of external port gpio_en_agc port mentioned in frequency hopping wiki page? In design i built using matlab flow as described in wiki guide, this port appears to be disconnected. I'm not sure if this was expected.
Its the pin which connects to the AGC control of the transceiver. If you want to know what external pins do like at the constraints file for the design and the physical pins are documented in the UG-570 document in the design files for the transceiver.