rx/tx fastlock control from FPGA


I want to control fastlock profiling from FPGA.

I'm using adrv9361-z7035 with linux OS on PS side. I have read in ad9361 reference manual (ug570) that CTRL_IN pins are used to select the desired stored profile. but i'm confused how can i access these pins in hdl design like Micheal suggested here https://ez.analog.com/linux-device-drivers/linux-software-drivers/f/q-a/87329/understanding-ad9361-iiostream-c-example/150200#150200

I have checked https://github.com/analogdevicesinc/linux_image_ADI-scripts/blob/master/test_tx_fastlock_pinctrl.sh example. I removed the debug messages and sleep command to minimize the delays but still it's timing performance is not stable. selecting 8 stored profile takes 13 u to 70 u seconds and this time is not stable. secondly my fastlock profile changing is dependent on hdl signals so i think i would be better to control fastlock profiles from hdl. 

can u help me here. 

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