Using a single channel on an ad9361 to receive, there are 12-bits of I and 12-bits of Q. In 2016_R2 we packed some extra data into the upper four bits of I and Q. In 2018_R2 we are using a simliar method but are suspecting it is being overwritten with a sign extension of the 12th bit. Our logic occurs before the CPack module. Is there anything new that would be causing this problem?